Follow Us On Twitter
News / Events
Press Releases
Shows & Events
Media Resources
About Products Applications Technology Corner Ruggedization News/Events

New Proteus-V6: Two 10-bit Channels at up to 5 GSPS in a Single Slot

Kansas City, MO – May 26, 2011 – At the 2011 IEEE Radar Conference, TEK Microsystems, Incorporated, the leading supplier of VME and VXS-based signal acquisition, generation and FPGA-based processing products, announced initial shipments of the QuiXilica Proteus-V6, the first product to combine 5 GSPS signal acquisition with Virtex-6 processing for VME and VXS based applications. The new Proteus-V6 combines three Xilinx Virtex-6 FPGAs with two e2v EV10AQ190 10-bit A/D converters, supporting either two channels at 5 GSPS, four channels at 2.5 GSPS, or eight channels at 1.25 GSPS, with sample accurate synchronization across multiple boards. Like previous generations of QuiXilica products based on Virtex II Pro and Virtex 5 technology, the Proteus-V6 is compatible with legacy VME systems as well as newer ANSI/VITA 41 VXS based systems in both laboratory and deployed / rugged applications.

“Tekmicro is committed to providing our customers with the widest range of A/D and D/A options combined with the best available FPGA processing technology for interoperable systems using deployable form factors such as VME and VXS. The new Proteus-V6 is another industry first for Tekmicro, combining the fastest available 10-bit ADC with our QuiXilica-V6 baseboard to create the highest density Virtex-6 solution for 6U legacy systems at these sample rates”, comments Andrew Reddig, CEO / CTO of Tekmicro. “The combination of 5 GSPS ADCs with sample accurate synchronization enables multichannel coherent systems with up to 5 GHz sampling, supporting surveillance, ELINT and N-channel DF applications that were previously not possible using COTS products.”

Fastest 10-bit ADC Converters
The Proteus-V6 has two e2v EV10AQ190 ADC devices, providing 10-bit resolution of either two channels at 5 GSPS, four channels at 2.5 GSPS, or eight channels at 1.25 GSPS. The ADC provides an Effective Number of Bits (ENOB) of 7.2 along with SFDR of 55 dBc when using a 1.2 GHz input. Both ADCs operate from a common clock and have an associated trigger / gate signal to support coherent processing across multiple Proteus-V6 boards in a system.

Proteus-V6 Raises the Bar on FPGA Density

The Proteus-V6 has three, highly connected, Xilinx Virtex-6 FPGA sites as shown in the attached block diagram. The two front-end FPGAs are attached directly to the A/D converters, providing a simple and direct high speed connection from the ADC to the FPGA. The third FPGA can be used to support additional processing, and also any required protocol support for either front panel or backplane interfaces.

All of the FPGA sites use the FF1759 package, which supports both LXT devices, optimized for high density logic, as well as SXT devices, optimized for digital signal processing. Each of the three FPGA sites can support the devices shown in Table 1 below.


FPGA Device
Logic Slices
DSP Slices
                                                Table 1: Proteus-V6 FPGA Device Options

The options available with Xilinx Virtex-6 FPGA technology expand both the range of options and the maximum processing density, while improving both performance and power efficiency. Figure 1 below shows the relative logic and DSP processing capability for the Proteus-V5 and V6 products. The Proteus options are shown in both minimum and maximum FPGA density configurations for each family.

                              Figure 1: Proteus FPGA Processing Capability from V5 to V6. 

Memory Resources
Each front end FPGA on the Proteus-V6 has two DDR3 memory banks, each with capacity of 1 GB and 6.4 GB/s of bandwidth, supporting full rate DRFM type applications for each input stream. The back end FPGA has an additional two banks of DDR3 memory along with two banks of QDR II+ memory for additional flexibility.

Network Interconnect
The Proteus-V6 provides a rich set of network interconnect options for both control and data plane communications. An onboard Gigabit Ethernet switch provides an integrated LAN-on-board network which connects the front panel interface, backplane interfaces, FPGA nodes, and system management processor into a local area network for control and status monitoring. The VXS backplane fabric interface can also support dual 10 Gigabit Ethernet interconnect using 10GBASE-KX4 interfaces with appropriate protocol cores in the back end FPGA.

Serial Interconnect
The Proteus-V6 supports 12 full duplex high speed fiber optic connections through the front panel along with 8 to 12 full duplex high speed fabric connections through the VXS P0 connector. Each Virtex-6 GTX transceiver supports up to 6.4 Gbps using either 8B/10B or 64/66 encoding, increasing the effective data rate by almost 2.5x per link over Virtex-5 GTP based solutions. When all front panel and backplane links are utilized, the Proteus-V6 supports total aggregate bandwidth of 37 GB/s (18.5 GB/s in each direction) to other off board processing resources. With suitable IP cores instantiated in the user’s application firmware code, a wide range of standard communication protocols across the high speed serial physical layer can be supported, including PCI Express, Serial FPDP, 1 and 10 Gigabit Ethernet and Aurora.

System Management
The QuiXilica-V6 architecture incorporates a next generation system management processor for bitstream management, board sanitization, power and thermal monitoring, built-in-test and extended diagnostics. The system management processor supports both I2C and Gigabit Ethernet interfaces to support both VITA-46.11-style system management as well as network-based protocols. All system management functions may also be accessed through the VMEbus interface for legacy applications that require a VME-based control architecture.

Ruggedization Support for Deployed Applications
The Proteus-V6 is available for a wide range of operating environments, including commercial grade, rugged air and conduction cooled, allowing the card to be used for both laboratory and deployed requirements in both VME and VXS systems. >For more information on rugged products.

Comprehensive Developers Kit Speeds Time To Market
All QuiXilica-V6 products are supported by a comprehensive Developer’s Kit that includes interface IP cores for all onboard resources along with Tekmicro’s QuiXtream network toolkit for rapid application development using network-enabled FPGAs. Reference designs are included, with source code, to support quick prototyping of user applications with minimal learning curve. The QuiXilica-V6 Developer’s Kit maintains common APIs across ADCs and FPGA families, supporting rapid, easy migration of existing V5 applications to V6 technology.

Initial shipments of the Proteus-V6 were delivered in May 2011. Standard delivery times are 8 to 12 weeks ARO.

> More Info: Proteus V6 Data Sheet

About TEK Microsystems, Incorporated.
Founded in 1981 and headquartered in Chelmsford, Massachusetts, Tekmicro designs, manufactures and delivers a wide range of advanced high-performance boards and systems for embedded real-time signal acquisition, generation, processing, storage and recording. Tekmicro provides both commercial and rugged grade products which are used in real-time systems designed for a wide range of defense and intelligence applications such as C4ISR, signals intelligence, electronic warfare and radar.

For more information or to have a representative contact you please complete the information below.