Follow Us On Twitter
News / Events
Press Releases
Shows & Events
Media Resources
About Products Applications Technology Corner Ruggedization News/Events

Highest available channel count plus Virtex-6 FPGAs for VME / VXS systems

Nashua, NH – June 23, 2011 – At the MILESTONE 2011 conference today, TEK Microsystems, Inc., the leading supplier of VME and VXS-based signal acquisition, generation and FPGA-based processing products, announced the QuiXilica Aries-V6, the first product to combine ten 16-bit 250 MSPS signal acquisition with Virtex 6 processing for VME and VXS based applications.
The combination of ten of the fastest available 16-bit resolution A/D converters with three Virtex-6 FPGAs sets new records in both channel and processing density for 6U signal acquisition and processing products, enabling systems with up to 180 coherent channels and 130 TeraMAC/s of processing in a single chassis. Like previous generations of QuiXilica products based on Virtex II Pro and Virtex 5 technology, the Aries-V6 is compatible with legacy VME systems as well as newer ANSI/VITA 41 VXS based systems in both laboratory and deployed / rugged applications.

“Tekmicro is committed to not only providing our customers with the widest range of A/D and D/A options combined with the best available FPGA processing technology but also to continuously raising the performance bar in deployable form factors such as VME and VXS. The new Aries-V6 extends our 16-bit digitization range up to 250 MSPS with up to 10 channels in a single 6U slot”, comments Andrew Reddig, CEO / CTO of Tekmicro. “Our previous generation Tarvos-V5 card is already designed into multiple deployed programs across a range of applications, and those customers can now use Aries-V6 to support 67% more channels and 50% more signal processing capability per channel within the same size, weight and power envelope, leveraging their investment in the QuiXilica signal processing architecture across multiple applications, programs and technology refresh cycles.”

High Bandwidth 16-bit ADC Converters
The Aries-V6 has ten Analog Devices AD9467 ADC converters, providing 16-bit resolution at sample rates up to 250 MSPS with an input bandwidth of 500 MHz. The ADC provides an Effective Number of Bits (ENOB) of 12.1 along with typical SFDR of 95 dBc and SNR of 74 dBFS when using a 97 MHz input. Each 6U card has a single clock and trigger input which is used for all input channels. The trigger signal may be used to support coherent processing across multiple Aries-V6 boards in a system, with up to 180 channels in a single chassis.

Aries-V6 Raises the Bar on FPGA Density
The Aries-V6 has three, highly connected, Xilinx Virtex-6 FPGA sites as shown in the attached block diagram. The two front-end FPGAs are attached directly to the A/D converters, providing a simple and direct high speed connection for signal processing of the input data streams. The third FPGA can be used to support additional processing, and also any required protocol support for either front panel or backplane interfaces.

All of the FPGA sites use the FF1759 package, which supports both LXT devices, optimized for high density logic, as well as SXT devices, optimized for digital signal processing. Each of the three FPGA sites can support the devices shown in Table 1 below.

FPGA Device
Logic Slices
DSP Slices

Table 1: Aries-V6 FPGA Device Options

The options available with Xilinx Virtex-6 FPGA technology expand both the range of options and the maximum processing density, while improving both performance and power efficiency. Figure 1 below shows the relative logic and DSP processing capability for the Tarvos-V5 and Aries-V6 products. The options are shown in both minimum and maximum FPGA density configurations for each family.

Figure 1: FPGA Processing Capability from Tarvos-V5 to Aries-V6

Memory Resources
Each front end FPGA on the Aries-V6 has two DDR3 memory banks, each with capacity of 1 GB and 6.4 GB/s of bandwidth, supporting simultaneous full rate DRFM type applications and snapshot data capture for each input stream. The back end FPGA has an additional two banks of DDR3 memory along with two banks of QDR II+ memory for additional flexibility.

Network Interconnect
The Aries-V6 provides a rich set of network interconnect options for both control and data plane communications. An onboard Gigabit Ethernet switch provides an integrated LAN-on-board network which connects the front panel interface, backplane interfaces, FPGA nodes, and system management processor into a local area network for control and status monitoring. The VXS backplane fabric interface can also support dual 10 Gigabit Ethernet interconnect using 10GBASE-KX4 interfaces with appropriate protocol cores in the back end FPGA.

Serial Interconnect
The Aries-V6 supports 12 full duplex high speed fiber optic connections through the front panel along with 8 to 12 full duplex high speed fabric connections through the VXS P0 connector. Each Virtex-6 GTX transceiver supports up to 6.4 Gbps using either 8B/10B or 64/66 encoding, increasing the effective data rate by almost 2.5x per link over Virtex-5 GTP based solutions. When all front panel and backplane links are utilized, the Aries-V6 supports total aggregate bandwidth of 37 GB/s (18.5 GB/s in each direction) to other off board processing resources. With suitable IP cores instantiated in the user’s application firmware code, a wide range of standard communication protocols across the high speed serial physical layer can be supported, including PCI Express, Serial FPDP, 1 and 10 Gigabit Ethernet and Aurora.

System Management
The QuiXilica-V6 architecture incorporates a next generation system management processor for bitstream management, board sanitization, power and thermal monitoring, built-in-test and extended diagnostics. The system management processor supports both I2C and Gigabit Ethernet interfaces to support both VITA-46.11-style system management as well as network-based protocols. All system management functions may also be accessed through the VMEbus interface for legacy applications that require a VME-based control architecture.

Ruggedization Support for Deployed Applications
The Aries-V6 is available for a wide range of operating environments, including commercial grade, rugged air and conduction cooled, allowing the card to be used for both laboratory and deployed requirements in both VME and VXS systems. >For more information on rugged products.

Comprehensive Developers Kit Speeds Time To Market
All QuiXilica-V6 products are supported by a comprehensive Developer’s Kit that includes interface IP cores for all onboard resources along with Tekmicro’s QuiXtream network toolkit for rapid application development using network-enabled FPGAs. Reference designs are included, with source code, to support quick prototyping of user applications with minimal learning curve. The QuiXilica-V6 Developer’s Kit maintains common APIs across ADCs and FPGA families, supporting rapid, easy migration of existing V5 applications to V6 technology.

Aries-V6 products are available now with standard delivery times of 8 to 12 weeks ARO.

>More Info:  Aries-V6 Data Sheet

About TEK Microsystems, Incorporated.
Founded in 1981 and headquartered in Chelmsford, Massachusetts, Tekmicro designs, manufactures and delivers a wide range of advanced high-performance boards and systems for embedded real-time signal acquisition, generation, processing, storage and recording. Tekmicro provides both commercial and rugged grade products which are used in real-time systems designed for a wide range of defense and intelligence applications such as C4ISR, signals intelligence, electronic warfare and radar.


For more information or to have a representative contact you please complete the information below.