TEK MICROSYSTEMS COMBINES 12-BIT A/D WITH VIRTEX-6 BASED SIGNAL PROCESSING FOR VME / VXS SYSTEMS
Eight 12-bit channels 550 MSPS with 2.3 GHz full power bandwidth
Chelmsford, MA – June 16, 2011 – TEK Microsystems, Incorporated, the leading supplier of VME and VXS-based signal acquisition, generation and FPGA-based processing products, has announced and begun initial shipments of the QuiXilica Pallene-V6, the first product to combine high fidelity 12-bit 550 MSPS signal acquisition with Virtex 6 processing for VME and VXS based applications. The new Pallene-V6 combines three Xilinx Virtex-6 FPGAs with Texas Instruments ADS54RF63 12-bit A/D converters, supporting eight channels at up to 550 MSPS with sample accurate synchronization across multiple boards. Like previous generations of QuiXilica products based on Virtex II Pro and Virtex 5 technology, the Pallene-V6 is compatible with legacy VME systems as well as newer ANSI/VITA 41 VXS based systems in both laboratory and deployed / rugged applications.
“Tekmicro is committed to providing our customers with the widest range of A/D and D/A options combined with the best available FPGA processing technology for interoperable systems using deployable form factors such as VME and VXS. The new Pallene-V6 adds another option for 12-bit digitization, complementing our Atlas-V6 with a 12-bit option with improved SFDR and SNR along with very high input bandwidth for applications that don’t require Atlas’s gigasample rates”, comments Andrew Reddig, CEO / CTO of Tekmicro. “By offering the widest range of ADC solutions, Tekmicro gives our customers a choice of solutions for their specific applications, allowing each customer to trade off resolution, sample rate and input bandwidth as necessary.”
High Fidelity 12-bit ADC Converters
The Pallene-V6 has eight Texas Instruments ADS54RF63 ADC devices, providing 12-bit resolution at sample rates up to 550 MSPS with an input bandwidth of 2.3 GHz. The ADC provides an Effective Number of Bits (ENOB) of 9.7 along with typical SFDR of 75 dBc and SNR of 62 dBFS when using a 450 MHz input. When taking advantage of the wide input bandwidth, the ADC still provides ENOB of 8.7, SFDR of 57 dBc and SNR of 59 dBFS using a 1.3 GHz input.
Each group of four channels can use independent clock and trigger inputs or can be configured to share a common clock and trigger. The trigger signal may be used to support coherent processing across multiple Pallene-V6 boards in a system, with up to 144 channels in a single chassis.
Pallene-V6 Raises the Bar on FPGA Density
The Pallene-V6 has three, highly connected, Xilinx Virtex-6 FPGA sites as shown in the attached block diagram. The two front-end FPGAs are attached directly to the A/D converters, providing a simple and direct high speed connection from the ADCs to the FPGA. The third FPGA can be used to support additional processing, and also any required protocol support for either front panel or backplane interfaces.
All of the FPGA sites use the FF1759 package, which supports both LXT devices, optimized for high density logic, as well as SXT devices, optimized for digital signal processing. Each of the three FPGA sites can support the devices shown in Table 1 below.
Table 1: Pallene-V6 FPGA Device Options
The options available with Xilinx Virtex-6 FPGA technology expand both the range of options and the maximum processing density, while improving both performance and power efficiency. Figure 1 below shows the relative logic and DSP processing capability for the Pallene-V5 and V6 products. The Pallene-V6 options are shown in both minimum and maximum FPGA density configurations for each family.
Figure 1: Pallene FPGA Processing Capability from V5 to V6
Each front end FPGA on the Pallene-V6 has two DDR3 memory banks, each with capacity of 1 GB and 6.4 GB/s of bandwidth, supporting full rate DRFM type applications for each input stream. The back end FPGA has an additional two banks of DDR3 memory along with two banks of QDR II+ memory for additional flexibility.
The Pallene-V6 provides a rich set of network interconnect options for both control and data plane communications. An onboard Gigabit Ethernet switch provides an integrated LAN-on-board network which connects the front panel interface, backplane interfaces, FPGA nodes, and system management processor into a local area network for control and status monitoring. The VXS backplane fabric interface can also support dual 10 Gigabit Ethernet interconnect using 10GBASE-KX4 interfaces with appropriate protocol cores in the back end FPGA.
The Pallene-V6 supports 12 full duplex high speed fiber optic connections through the front panel along with 8 to 12 full duplex high speed fabric connections through the VXS P0 connector. Each Virtex-6 GTX transceiver supports up to 6.4 Gbps using either 8B/10B or 64/66 encoding, increasing the effective data rate by almost 2.5x per link over Virtex-5 GTP based solutions. When all front panel and backplane links are utilized, the Pallene-V6 supports total aggregate bandwidth of 37 GB/s (18.5 GB/s in each direction) to other off board processing resources. With suitable IP cores instantiated in the user’s application firmware code, a wide range of standard communication protocols across the high speed serial physical layer can be supported, including PCI Express, Serial FPDP, 1 and 10 Gigabit Ethernet and Aurora.
The QuiXilica-V6 architecture incorporates a next generation system management processor for bitstream management, board sanitization, power and thermal monitoring, built-in-test and extended diagnostics. The system management processor supports both I2C and Gigabit Ethernet interfaces to support both VITA-46.11-style system management as well as network-based protocols. All system management functions may also be accessed through the VMEbus interface for legacy applications that require a VME-based control architecture.
Ruggedization Support for Deployed Applications
The Pallene-V6 is available for a wide range of operating environments, including commercial grade, rugged air and conduction cooled, allowing the card to be used for both laboratory and deployed requirements in both VME and VXS systems. >For more information on rugged products.
Comprehensive Developers Kit Speeds Time To Market
All QuiXilica-V6 products are supported by a comprehensive Developer’s Kit that includes interface IP cores for all onboard resources along with Tekmicro’s QuiXtream network toolkit for rapid application development using network-enabled FPGAs. Reference designs are included, with source code, to support quick prototyping of user applications with minimal learning curve. The QuiXilica-V6 Developer’s Kit maintains common APIs across ADCs and FPGA families, supporting rapid, easy migration of existing V5 applications to V6 technology.
Initial shipments of the Pallene-V6 were delivered in May 2011. Standard delivery times are 8 to 12 weeks ARO.
About TEK Microsystems, Incorporated.
Founded in 1981 and headquartered in Chelmsford, Massachusetts, Tekmicro designs, manufactures and delivers a wide range of advanced high-performance boards and systems for embedded real-time signal acquisition, generation, processing, storage and recording. Tekmicro provides both commercial and rugged grade products which are used in real-time systems designed for a wide range of defense and intelligence applications such as C4ISR, signals intelligence, electronic warfare and radar.
For more information or to have a representative contact you please complete the information below.