The QuiXilica VXS family are flexible analog and digital VITA 41.0 VXS I/O products. High performance analog and digital I/O front ends are combined with a scalable FPGA based processing architecture. Memory and inter-processor communication resources are optimized for very high performance real time DSP applications. QuiXilica includes development kits, FPGA cores and software, giving users power and flexibility while retaining consistency and ease of use. These products can be used without a backplane if desired.

The QuiXilica V5 Architecture meets the needs of demanding sensor-processing applications across a range of environments. The QuiXilica V5 architecture uses the latest field programmable gate array (FPGA) based processors - the Xilinx Virtex®-5 family, advanced DDR3 SDRAM, and the latest communications technologies available. Full ruggedization has been designed into the architecture from the outset to provide products suitable for harsh demanding environments and deployed systems.

For a complete information download the QuiXilica V5 whitepaper.

ADCs and DACs at a Glance


PRODUCT	SAMPLE RATE	# OF CHANNELS	RESOLUTION	FPGA	FRONT PANEL I/O	MEMORY	FORM FACTOR
Charon-V5	1.2 GSPS	8 DAC	12-bits DAC	3 V-5 SXT, LXT or FXT	6 front panel high speed serial ports at 3.75 Gb/s each	3 GB DDR3 6 banks 38.4 GB/s	6U VXS 6U VME
Titan-V5	1.0 GSPS Input 1.2 GSPS Output	4 ADC 4 DAC	12-bits ADC 14-bits DAC	3 V-5 SXT, LXT or FXT	6 front panel high speed serial ports at 3.75 Gb/s each	3 GB DDR3 6 banks 38.4 GB/s	6U VXS 6U VME
Atlas-V5	1.0 GSPS	8 ADC	12-bits ADC	3 V-5 SXT, LXT or FXT	6 front panel high speed serial ports at 3.75 Gb/s each	3 GB DDR3 6 banks 38.4 GB/s	6U VXS 6U VME
Orion-V5	3.0 GSPS	2 DAC	12-bits DAC	3 V-5 SXT, LXT or FXT	6 front panel high speed serial ports at 3.75 Gb/s each	3 GB DDR3 6 banks 38.4 GB/s	6U VXS 6U VME
Triton-V5	2.2 GSPS Input 3.0 GSPS Output	1 ADC 1 DAC	10-bits ADC 12-bits DAC	3 V-5 SXT, LXT or FXT	6 front panel high speed serial ports at 3.75 Gb/s each	3 GB DDR3 6 banks 38.4 GB/s	6U VXS 6U VME
Neptune-V5	2.2 GSPS	2 ADC	10-bits ADC	3 V-5 SXT, LXT or FXT	6 front panel high speed serial ports at 3.75 Gb/s each	3 GB DDR3 6 banks 38.4 GB/s	6U VXS 6U VME
Tarvos-V5	185 MSPS	6 ADC 1 DAC	16-bits ADC 16-bits DAC	3 V-5 SXT, LXT or FXT	6 front panel high speed serial ports at 3.75 Gb/s each	3 GB DDR3 6 banks 38.4 GB/s	6U VXS 6U VME
Triton VXS	2 GSPS	1 ADC 1 DAC	12-bits ADC 12-bits DAC	V2 Pro 70	2x Front Panel SFP Slots for 2.5 Gb/s Fiber or Copper Transceivers	5 GB DDR 4 banks 512 MB/bank	6U VXS 6U VME
Tarvos VXS	160 MSPS	6 DAC 1 ADC	16-bits DAC 16-bits ADC	3 V-5 SXT, LXT or FXT	2x Front Panel SFP Slots for 2.5 Gb/s Fiber or Copper Transceivers	5 GB DDR 4 banks 512 MB/bank	6U VXS 6U VME
Neptune VXS	2 GSPS	2 ADC	10-bits ADC	V2 Pro 70	2x Front Panel SFP Slots for 2.5 Gb/s Fiber or Copper Transceivers	5 GB DDR 4 banks 512 MB/bank	6U VXS 6U VME
Janus VXS	500 MSPS	7 DAC	16-bits DAC	V2 Pro 70	2x Front Panel SFP Slots for 2.5 Gb/s Fiber or Copper Transceivers	2x DDR SDRAM banks 512 MB/bank 2x DDR SDRAM SODIMM slots, up to 2 GB each	6U VXS 6U VME
Callisto VXS	N/A	12 (digital)	N/A	V2 Pro 70 (5x)	2x Front Panel SFP Slots for 2.5 Gb/s Fiber or Copper Transceivers	Front panel - up to 12x 2.5 Gb/s links through fiber or copper SFP Transceivers	6U VXS
Venus VXS	105 MSPS	5 ADC	14-bits	V2 Pro 70	2x Front Panel SFP Slots for 2.5 Gb/s Fiber or Copper Transceivers	5 GB DDR 4 banks 512 MB/bank	6U VXS 6U VME

QuiXilica Family - Virtex-5 based

Charon-V5
•

Eight 12-bit DAC Outputs at 1.2 GSPS Each
• Up to 144 Channels in a Single VXS chassis
• Sample Accurate Synchronization Across Multiple Boards
• Six Digital IO Channels Running at Up to 3.75 Gb/s Using One QSFP and Two SFP+ Front Panel Connections
• Three Xilinx Virtex-5 FPGAs: LXT, SXT or FXT for Each Location
• Three GB DDR3 SDRAM Memory, (one GB per FPGA)
• Comprehensive Developer’s Kit Provided Including FPGA Interface Cores, QuiXtart FPGA Utilities, Software and Reference Design
• Ruggedization Designed in For Demanding Deployed Applications

Titan-V5
Titan-V5 VXS from Tekmc

• Eight Channels
• Four 12-bit ADC inputs at 1 GSPS ea
• Four 14-bit DAC outputs at 1.2 GSPS ea
• Ultra low Latency
• Sample Accurate Synchronization Across Multiple Boards
• Six Digital IO Channels Running at Up to 3.75 Gb/s Using One QSFP and Two SFP+ Front Panel Connections
• Three Xilinx Virtex-5 FPGAs: LXT, SXT or FXT for Each Location
• Three GB DDR3 SDRAM Memory, (one GB per FPGA)
• Comprehensive Developer’s Kit Provided Including FPGA Interface Cores, QuiXtart FPGA Utilities, Software and Reference Design
• Ruggedization Designed in For Demanding Deployed Applications

Atlas-V5
• Eight Channels: 12-bit ADC Input at 1 Gsps Ea
• Sample Accurate Synchronization Across Multiple Boards
• All Eight ADCs Clocked from a Common Input or Two Independent Clock Inputs for Groups of Four ADC Channels
• High Channel Count, Low Latency Data Routing and Large/Fast FPGA Processing
• Six Digital IO Channels Running at Up to 3.75 Gb/s Using One QSFP and Two SFP+ Front Panel Connections
• Three Xilinx Virtex-5 FPGAs: LXT, SXT or FXT for Each Location
• Three GB DDR3 SDRAM Memory, (one GB per FPGA)
• Comprehensive Developer’s Kit Provided Including FPGA Interface Cores, QuiXtart FPGA Utilities, Software and Reference Design
• Ruggedization Designed in For Demanding Deployed Applications

Triton-V5

• Two Channels: One 10-bit ADC Input at 2.2 Gsps, Co-located With One 12-bit DAC Output at up to 3.0 Gsps.
• Sample Accurate Synchronization Across Multiple Boards.
• ADC and DAC Can Use Common Clock
• Six Digital IO Channels Running at Up to 3.75 Gb/s Using One QSFP and Two SFP+ Front Panel Connections
• Three Xilinx Virtex-5 FPGAs: LXT, SXT or FXT for Each Location
• Three GB DDR3 SDRAM Memory, (one GB per FPGA)
• Comprehensive Developer’s Kit Provided Including FPGA Interface Cores, QuiXtart FPGA Utilities, Software and Reference Design
• Ruggedization Designed in For Demanding Deployed Applications

Orion-V5 VXS
• Two Channels: Two 12-bit DACs Output at up to 3.0 Gsps Each
• Sample Accurate Synchronization Across Multiple Boards.
• Phase-matched DAC Outputs
• Six Digital IO Channels Running at Up to 3.75 Gb/s Using One QSFP and Two SFP+ Front Panel Connections
• Three Xilinx Virtex-5 FPGAs: LXT, SXT or FXT for Each Location
• Three GB DDR3 SDRAM Memory, (one GB per FPGA)
• Comprehensive Developer’s Kit Provided Including FPGA Interface Cores, QuiXtart FPGA Utilities, Software and Reference Design
• Ruggedization Designed in For Demanding Deployed Applications

Tarvos-V5 VXS
• Seven Channels: Six 16-bit ADC Inputs at 185 Msps each, One 16-bit DAC Output at 185 Msps
• Six Digital IO Channels Running at Up to 3.75 Gb/s Using One QSFP and Two SFP+ Front Panel Connections
• Dual 4x Full Duplex VXS Links and Two Full Duplex VITA 41.6 Ethernet Links
• Three Xilinx Virtex-5 FPGAs: LXT, SXT or FXT for Each Location
• Three GB DDR3 SDRAM Memory, (one GB per FPGA)
• Comprehensive Developer’s Kit Provided Including FPGA Interface Cores, QuiXtart FPGA Utilities, Software and Reference Design
• A Measured 72.31 dBFS Noise Floor with Greater Than 95 dB of SFD
• Ruggedization Designed in For Demanding Deployed Applications

Neptune-V5 VXS
• 2 channel 10-bit 2.2 Gsps ADC
• 6 front panel high speed serial ports at 3.75 Gb/s each
• 1 GB DDR3 Memory per FPGA Superior SNR and SFDR
• Three Xilinx Virtex-5 SXT, LXT or FXT
• Convection or Conduction Cooled
• Dual 4x Full Duplex VXS Links
• 2x Full Duplex Vita 41.6 Ethernet Links
• Advanced Temperature and Current Monitoring
• QuiXstart FPGA Configuration System
• Developer’s Kit: FPGA interface Cores, Software and Reference Design
• VME/VXS form factor, VITA 41.0 Compliant

QuiXilica Digitizers at a Glance

Callisto VXS
• Five VC2VP50 FPGAs provide high bandwidth communications links
• High performance FPGA Based Communications management and processing platform
• Fits in Switch card position in VXS backplane
• High Performance FPGA Based Communications Management and Processing Platform

Triton VXS
• Dual Channel, 2 Gsps ADC and DAC Combo Digitizer
• 1x 10-bit 2 Gsps Atmel ADC/DMUX
• 1x 12-bit 2 Gsps Euvis MUX/DAC
• 2x Front Panel SFP Slots for 2.5 Gb/s Fiber or Copper Transceivers
• 2x DDR SDRAM SODIMM Slots, Up to 2 GB Each
• Large FPGA Processing Engine

Neptune VXS
• Dual Channel 2 Gsps ADC Digitizer
• 2x 10-bit 2 Gsps Atmel ADC/DMUX
• 2x Front Panel SFP Slots for 2.5 Gb/s Fiber/Copper Transceivers
• 2x DDR SDRAM SODIMM Slots, Up to 2 GB Each
• Large FPGA Processing Engine

Tarvos VXS
• 6x 16-bit 160 Msps ADC channels based on LTC2209
• One 16-bit 500 Msps DAC channel based on MAX5891
• 2x front-panel SFP slots for 2.5 Gb/s fiber or copper transceivers
• 2x on-board DDR SDRAM banks 512 MB/bank
• 2x DDR SDRAM SODIMM slots, up to 2 GB each
• Large FPGA Processing Engine

Janus VXS
• 7 x 16-bit 500 Msps DAC channels, based on MAX5891
• 2 x front-panel SFP slots for 2.5 Gb/s fiber or copper transceivers
• 2 x on-board DDR SDRAM banks, 512 MB per bank
• 2 x DDR SDRAM SODIMM slots, up to 2 GB each
• Large FPGA Processing Engine