High Speed Serial Communication using Rocket IO technology.

- Up to 2.5 Gbits/s link speed
- Up to 80 Gbits/s aggregate data rate on XC2VP70
- High speed point to point serial link
- Interfaces directly to parallel FPDP

The Quixilica® Serial Front Panel Data Port core provides a Parallel Front Panel Data Port interface to the Serial Front Panel Data Port communications protocol. It uses Xilinx Rocket IO technology to provide 8b/10b encoded data transfer at up to 2.5Gbits/s.

Flow control is supported over a bi-directional link i.e. a link that has both transmitter and receiver at each end. This can be used to prevent data loss due to buffer overflow at the receiver.

The Core supports the unframed, single frame, fixed size repeating frame and dynamic size repeating frame formats as specified in the Parallel FPDP standard. These are mapped onto the Serial FPDP frame formats appropriately.

Features

    * Parallel FPDP interface, based on the American National Standard for Serial Front Panel Data Port ANSI/VITA 17.1-2003
    * Bi-directional Data Flow at 1.06Gbits/s, 2.02Gbits/s or 2.5Gbits/s
    * Optional flow-control to prevent data loss
    * Multiple frame formats, compatible with the Standard for Serial Front Panel Data Port ANSI/VITA 17.1-2003
    * Optional CRC