The QuiXxilica Tarvos VXS is part of the QuiXilica VXS family of FPGA based processing hardware. The QuiXilica VXS family provides a complete range of flexible analog and digital IO products in the VITA 41.0 VXS form factor. The product range couples high performance analog and digital IO front ends with a scalable FPGA based processing architecture. Memory and inter-processor communications resources have been optimized to address the requirements of very high performance real time digital signal processing applications. QuiXilica is supported by a range of development kits, FPGA cores and software, providing users with power and flexibility while retaining consistency and ease of use.

Key applications for the Tarvos VXS include radar, electronic warfare, software radio, Automatic test equipment, scientific instrumentation and telecommunications.

Features:
• 6x 16-bit 160 MSPS ADC channels based on LTC2209
• One 16-bit DAC channel based on MAX5891
• Xilinx XC2VP70 FPGA
• VME/VXS form factor, VITA 41.0 compliant, 8 x 3.125 Gbps serial I/O links
• 2x front-panel SFP slots for 2.5 Gbps fiber or copper transceivers
• 2x on-board DDR SDRAM banks  512 MB/bank
• 2x DDR SDRAM SODIMM slots, up to 2 GB each   
• Quixstart flexible FPGA configuration system
• Developer’s Kit Available: FPGA interface cores, software and reference design

Hardware
The Tarvos VXS is a 6U form factor card that can be employed
as a payload card as defined in the VITA 41.0 VXS specification.
The card can also be deployed in a standard VME 64 chassis
if the P0 connector is not populated. The VME 64 interface is
used only for powering the card.

The VME bus interface itself is not implemented. Control and
high speed data IO for the card will be implemented using the
high speed serial links available on the front panel and/or the
backplane P0 connector. The card can also be used standalone
(i.e. without a backplane).

The Tarvos VXS is supplied with a standard FPGA bitstream
and Windows based software application for a multi-channel,
data capture download and display system. A standard
Gigabit Ethernet link to the front panel is used to interface the
card to the host PC.

A hardware reference manual provides users with sufficient
detail to develop their own FPGA based applications. For rapid
development, an additional Developer’s Kit can be purchased
which contains FPGA interface cores, software and source
code for the data capture download and display system as a
reference design.