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Neptune-V5 (2 10-bit ADC)
  • Overview
  • Details
  • Performance Specifications

Overview

The QuiXilica Neptune-V5 VXS is an ANSI VITA 41-compliant dual channel high speed digitizer board based on the QuiXilica V5 architecture from TEK Microsystems. Designed to meet the needs of demanding sensor-processing applications across a range of environments, the Neptune-V5 employs three Virtex®-5 processors, advanced DDR3 SDRAM, and the latest communications technologies available.
 

QuiXilica Neptune-V5
2 x 2.2 GSPS x 10-bit ADC

Full ruggedization has been designed into the architecture providing full support for harsh environments. For specifications go to the Ruggedization page.Rugged Embedded Board

The Neptune-V5 design logically follows and meets the data flow requirements of advanced applications and does the job more efficiently than anything else available.

Widely adopted standards and the very latest in technology gives customers the optimum in performance and investment protection.

Software support for a range of open standards and protocols is provided including Gigabit Ethernet, Serial FPDP (ANSI VITA 17.1 and 17.2) and Fibre Channel. For inter-FPGA and inter-board communications, protocol support is provided for Xilinx Aurora and PCI Express. Our approach to the architecture focuses on the sensor IO processing and allows more efficient use the three Virtex-5 processors than competitive offerings of up to seven FPGAs resulting in a lower price point and reduced power consumption.

The two SFP+ sites and one QSFP site on the front panel utilize standard fiber optic or 1000BaseT modules provide the physical layer support for standard protocols such as Gigabit Ethernet, Serial FPDP (ANSI VITA 17.1 & 17.2), and Fibre Channel. Alternative SFP modules can be supplied by contacting the factory.

 Virtex-5 FPGAs

Neptune-V5 uses three Xilinx Virtex-5 FPGAs to provide maximum high bandwidth processing and system configuration flexibility.

Depending on the application, customers can select from:

• Virtex-5 LXT Platform - Optimized for high-performance logic with low-power serial connectivity

• Virtex-5 SXT Platform - Optimized for DSP and memory-intensive applications with low-power serial connectivity

• Virtex-5 FXT Platform - Optimized for embedded processing and memory-intensive applications with highest-speed serial connectivity

In a typical configuration shown above two Xilinx Virtex-5 SX95T FPGAs interface between the AT84AS008 based ADC’s, memory and I/O resources to provide the user with a platform for implementing high performance real time processing. The IO FPGAs A and B can be any Virtex-5 FF1136 device. The back-end Comms FPGA can be any 1738 device which provides additional resources for implementing DSP and interfaces to the VXS backplane. All FPGAs are interconnected by wide parallel LVDS busses and also via high speed serial links using the Xilinx Rocket IO MGTs.

VXS Backplane High Speed Serial IO

The Neptune-V5 can be used as a VITA 41.0 payload card. Up to eight high speed serial links of up to 3.125 Gb/s full duplex data rates are supported via the VITA 41.0 standard MultiGig RT2 P0 connector. Custom or standard communication protocols can be run over these links with appropriate firmware in the FPGA.

QuiXstart FPGA Configuration

A number of options are available for configuring the FPGA on the Neptune-V5. For development purposes, a JTAG connection is available that allows users to configure the FPGA via standard Xilinx development tools. On board flash is available and can configure the FPGA on power up. Tekmicro’s QuiXstart tool also supports flexible configuration of the FPGA through a Gigabit Ethernet link from a remote server after a power up or reset event.

ADCs

Two e2v AT84AS008 10-bit Analog to Digital Converters (ADCs) are provided on a Neptune-V5, each capable of operating at sampling rates of 2.2 Gsps (Gigasamples per second). The ADCs are configured as single ended AC coupled, although alternate configurations can be provided A data ready signal output is supplied along with the data bus signals and is used to latch the data into the FPGA. Control functions on each ADC such as sampling point adjustment, gain adjustment, and input DC bias adjustment can be accessed from the FPGA, through a two-wire, I2C-compatible interface. The same interface can adjust the relative phase of the data and the data ready signal at the output of the DMUX.

High Speed Trigger Input

Trigger firmware can be implemented in the FPGA to fully synchronize data captures between multiple ADC channels on the same board or across multiple Neptune-V5 boards if required.

Memory

The Neptune-V5 has two independent banks of onboard double data rate (DDR3) SDRAM for each FPGA. providing a capacity of 512 MB in each bank, 1 GB total per FPGA. The onboard memory can be clocked at rates up to 400 MHz, 800 MHz double data rate. Optional 1 GB per bank DDR3 devices can provide a capacity of 2 GB total memory per FPGA.

System Monitoring

The Neptune-V5 board includes facilities to monitor current and temperature at various points on the board. Current monitoring of all main power rails is available. Die temperature monitoring of the three FPGAs and temperature monitoring of three locations on the PCB is also available. This allows a first level of protection to be implemented when the Neptune-V5 is operating in a variety of different environmental scenarios. The output from the sensors will also be available to users through the Comms FPGA firmware. The condition monitoring peripherals will share an I2C bus with the I2C bus from the Comms FPGA to the QSFP module.
 

Quantity: 1 or 2 via (4) SMA Connectors
Type: Single ended or differential.
Full Scale Input: -2dBm into 50Ω.
Input signal must be -2dBm within the first Nyquist band of the ADC to achieve full scale ADC conversion.

Front Panel Trigger Inputs
Quantity: 1 or 2 via (4) SMA Connectors
Type: LVDS (Optional: LVPECL)
Termination: LVDS 100Ω differential terminated (Optional: LVPECL)
Standalone: Independent Trigger inputs for each analog input
Master/Slave: Select Trigger MASTER, connect board-to-board connector to Trigger SLAVE

External Clock
Quantity: 1 or (2) via (2) SMA Connectors
Single ended 50Ω terminated
Input Power Range: 2dBm (min) to 10dB (max)

Operating Modes:
Clock Standalone / Master/Slave
Standalone: Use independent clock inputs for each analog input.
Master/Slave: Select clock MASTER, connect board-to-board connector to clock SLAVE

A/D Converters
Quantity: 1 or 2
Sampling Rate: 2.2 GSPS
Resolution: 10 bits
Type: e2v AT84AS008
Bandwidth: 3.3GHz at full power

Demultiplexer
Quantity: 1 or 2
Type: e2v AT84CS001
Demux Ratio: 1:4
Tunable Delay: -250ps to +250ps
Output Resolution: 10 bits

Memory
DDR3 SDRAM (2 banks per FPGA)
Size (STD): 512 MB per bank, 1 GB total per FPGA
Bus Width: 64bits
Speed: 400MHz, 800MHz double data rate

Front Panel High Speed Serial Interface
2x SFP+ Ports: Providing (2) high-speed serial connections. Range of standard protocols, including Gigabit Ethernet and FibreChannel.

1x QSFP Port:
A quadruple SFP connector, of four independent lanes of high-speed serial. The lanes may be bonded together.
Port supports a range of standard protocols: Gigabit Ethernet, Fibre Channel and 10-Gigabit Ethernet (via 4-lane XAUI).

JTAG Port
Access to Virtex-5 FPGAs is available via custom JTAG cable assembly that interfaces with JTAG programming cable.

Size:
Standard 6U VMEbus board, single slot; PCB:160mm (6.3”) x 233.5mm (9.2”)

Power:
+5V, +3.3V, ±12V from VME64 backplane. Power consumption is dependent on customer application. Power estimating tools available on request.