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I/O Interface : -JazzFiber-V5 Serial FPDP I/O Module | PowerRACE-2A | PowerRACE-2B | PowerRACE-3A
-JazzFiber-V5 Serial FPDP I/O Module : Atlas-V5 VXS Eight 12-bit ADCs at 1.0 GSPS Each | Calypso-V5 VXS 2 12-bit ADCs 3.2 GSPS | Charon-V5 VXS Eight 12-bit DACs at 1.2 GSPS Each | Neptune-V5 VXS Two 10-bit ADC at 2.2 GSPS Each | Orion-V5 VXS Two 12-bit DACs up to 4.0 GSPS | Proteus-V5 VXS Two 10-bit ADCs at 5 GSPS | Tarvos-V5 VXS Six 185 MSPS ADC, One DAC | Titan-V5 VXS Eight Channels: Four ADC, Four DAC | Triton-V5 VXS One 10-bit ADC Input at 2.2 GSPS | VXS Developers Kit
-JazzFiber-V5 Serial FPDP I/O Module : Callisto VXS Up to 16 Payload slots | Janus VXS | Neptune VXS | Tarvos VXS | Triton VXS | Venus VXS


-JazzFiber-V5 Serial FPDP I/O Module

Datasheet (PDF)

Key Features and Benefits

•    Four fiber optic interfaces at up to 6.25 Gb/s. Aggregate throughput of 25 Gb/s
    Xilinx Virtex 5 FPGA technology, including FXT devices
   “Classic” Serial FPDP plus VITA 17.2 extensions, including channel bonding, higher bit rates, and protocol enhancements
    512 MB of DDR3 memory with 6.4 GB/s of onboard throughput
    PMC interface with PCI-X 64-bit 133 MHz local bus
   XMC interface with PCI Express 1.0a x8 for 2 GB/s full duplex throughput
   Commercial, rugged air-cooled and rugged conduction-cooled options


Overview

The JazzFiber-V5™ Serial FPDP I/O Module provides a high speed connection between one or more external sensors and a processing or recording system using an open standard modular I/O architecture.  Each JazzFiber-V5 module supports four fiber optic interfaces, which can be used as separate Serial FPDP channels or aggregated into logical streams using the channel bonding capability of the emerging VITA 17.2 standard. Additional VITA 17.2 features including enhanced protocol and higher bit rates are also supported.

The JazzFiber-V5 is carefully designed to maximize performance in hardware, firmware, and software to support wirespeed throughput between external sensor(s) and the user’s baseboard.  Each element of the module’s design – fiber optic transceivers, FPGA, memory, and local bus/fabric interfaces – is optimized for maximum throughput to meet both current and future Serial FPDP requirements.  The hardware is supported with optimized firmware and software drivers for a range of operating environments, making the JazzFiber-V5 easy to drop in and get running quickly.

The JazzFiber-V5 is designed from the ground up to support both commercial and rugged environments – including conduction cooling. In a laboratory, deployed in a ground vehicle, onboard a ship, or in a UAV, the JazzFiber-V5 provides a common solution for every environment, no matter how demanding.

Front Panel I/O

The JazzFiber-V5 has four LC-style fiber optic transceivers mounted at the front panel of the module.  The fiber optic transceivers may be ordered with either single or multi-mode fiber interfaces at either 850 or 1310 nm wavelengths.  The baseline module supports baud rates of 2.5 Gb/s, with alternate speeds between 1.062 and 6.4 Gb/s available as options.

Table 1: Fiber Optic Interface Options

Wavelength

Cable 

Baud Rate

Max Distance

850 nm 

50 / 62.5 µm multimode

2.5 Gb/s

150 m

1300 nm

9 µm single mode

2.5 Gb/s

   2 km


Serial FPDP Protocol

The JazzFiber-V5 implements the ANSI/VITA 17.1-2003 Serial Front Panel Data Port (FPDP) protocol.  Serial FPDP provides low protocol overhead, support for synchronization primitives in the data stream and high efficiency.

The ANSI/VITA 17.1-2003 serial FPDP protocol supports baud rates of 1.062, 2.125, and 2.5 Gb/s, with net data rates up to 247 MB/s after data encoding and protocol overhead. VITA 17.2 serial FPDP protocol extensions support baud rates up to 6.25 Gb/s.
  Serial FPDP has been deployed in a wide range of sensor I/O applications and is a well established tool for moving large amounts of data between external sensors and signal or data processor systems. 
 
The latest generation of Serial FPDP is being finalized as VITA 17.2. It adds several enhancements to the protocol, including official support for higher baud rates, channel bonding, and protocol enhancements.  The JazzFiber-V5 supports many of the elements of 17.2. Tekmicro will continue to update firmware as the standard is finalized.

Table 2: Serial FPDP Throughput
# of Fibers Baud Rate Throughput
One 1.062 Gb/s 105 MB/s
One 2.5 Gb/s 
247 MB/s
One 6.4 Gb/s 633 MB/s
Four 2.5 Gb/s 997 MB/s
Four 6.4 Gb/s 2553 MB/s


Virtex 5 FPGA

The JazzFiber-V5 uses a Xilinx Virtex-5 FPGA to implement the interface protocol, memory buffering, DMA engines, and local bus/fabric interface.  The FPGA device selected depends on the number of channels and the serial baud rate, ranging from a two channel 2.5 Gb/s module using an LX50T, to a four channel 6.25 Gb/s module using an FX100T.

The FPGA bitstream is automatically loaded from onboard FLASH memory at power up.  Utilities are provided to program and verify FLASH memory to support bitstream updates in the field.


Figure 1: FPGA IP Block Diagram

DDR3 Memory Buffers

The JazzFiber-V5 uses the latest memory technology – DDR3 – to provide maximum memory throughput at 23% less power than DDR2 based memory.  With four independent memory banks clocked at 400 MHz each, the buffer memory subsystem provides aggregate throughput of 6.4 GB/s, supporting full rate deep FIFO buffering of the maximum 25 Gb/s fiber optic capability.  The baseline module has 512 MB of memory, which provides up to 500 ms of buffering at full 17.1 Serial FPDP rates, decoupling the module from local bus memory latencies.  The module will support memory capacities of up to 2 GB when higher density memory devices are available in 2009.

Technology Speed Power (per 1 GB/s)
DDR (JazzFiber)
133 MHz (2.1 GB/s) 2200mW
DDR2
333 MHz (5.3 GB/s) 290 mW
DDR3 (JazzFiber-V5) 400 MHz (6.4 GB/s)  
190 mW
Table 3: Comparison Serial FPDP Memory Buffer Technologies


Local Bus Interface

The JazzFiber-V5 provides two high performance local bus interfaces: PCI and PCI Express.  The PCI interface operates at up to 64-bit 133 MHz and is compatible with the IEEE 1386.1-2001 PCI Mezzanine Card (PMC) standard as well as ANSI/VITA 39-2003.

To provide maximum compatibility with legacy systems, an onboard PCI-to-PCI bridge is used to support legacy PCI carriers from 32-bit 33 MHz up to 64-bit 133 MHz with universal I/O signal level compatibility.  When used with a high performance carrier with a 64-bit 133 MHz bus, the PCI interface sustains up to 900 MB/s.

For the next generation of carrier card, the JazzFiber-V5  supports a local fabric interface using the PCI Express protocol.  The PCI Express interface is compatible with the VITA 42.0 Switched Mezzanine Card (XMC) base standard along with its PCI Express variant, ANSI/VITA 42.3-2006.  The PCI Express interface implements x1, x4, or x8 serial lanes at 2.5 Gb/s each with throughput up to 2.0 GB/s in each direction.

Table 4: Local Bus / Fabric Throughput
Standard Architecture Mode
Max Throughput
PCI  
Bus 
32 bit 33 MHz 133 MB/s
PCI-X
Bus 
64 bit 66 MHz 533 MB/s
PCI-X
Bus 
64 bit 133 MHz 1067 MB/s
PCI Express Fabric 1 x 2.5 Gb/s 2 x 250 MB/s
PCI Express Fabric 4 x 2.5 Gb/s 2 x 1000 MB/s
PCI Express Fabric 8 x 2.5 Gb/s 2 x 2000 MB/s


System Management

The JazzFiber-V5 includes system monitoring functions that monitor load current and operating temperature at key points on the card.  In the event of a fault condition, an alert is raised to the host for appropriate action. The system monitoring is also available through the XMC I2C interface for environments that implement IPMI capability.


Software Support

The JazzFiber-V5 includes driver support for Windows, Linux and VxWorks, allowing the module to be used in a wide range of target environments.  The software application programming interface (API) is common across all three operating environments, providing a reusable solution across both x86 and PowerPC platforms in many different form factors.  Please consult with the factory about host support for specific carriers, processors and operating environments.
The software drivers are tightly coupled to the onboard DMA controllers implemented in the Virtex-5 FPGA, providing independent control of each Serial FPDP transmit and receive stream.  The DMA engines support all of the Serial FPDP framing modes (unframed, fixed length and variable length), allowing the user application to easily support any type of Serial FPDP sensor.  Aggregation of 17.2-compliant channel bonded streams is handled transparently by the firmware, providing the software with a single “stream” interface to both single and multiple physical fiber streams.

Ruggedization

The JazzFiber-V5 is available in commercial, rugged air-cooled and rugged conduction cooled models.  All of the JazzFiber-V5 models are based on the same hardware design and reuse the same firmware and software, making it straightforward to move from a laboratory prototype to a deployed system.

Because the JazzFiber-V5 uses fiber optic I/O interfaces, the front panel interface is required to be available even in a conduction cooled environment.  This may require some tailoring of the carrier card in some applications – please consult the factory for more information about specific carrier cards.


Customization

The JazzFiber-V5 module is available as a customizable FPGA-based processing platform for applications that require additional flexibility. The QuiXmodule-V5 Fiber Optic I/O Module is available with an expanded range of FPGA devices (LX110T, LX155T, SX95T and FX100T) and can be used to implement alternate external I/O protocols as well as alternate local fabric interfaces such as Serial RapidIO (ANSI/VITA 42.2) and Xilinx Aurora (VITA 42.5).  Please
please consult the factory for more information.


PERFORMANCE SPECIFICATIONS

Fiber Optic I/O
Serial Baud Rate: 2.5 Gb/s standard, 1.062 to 6.25 Gb/s options available
Interface: 850 nm for 50 / 62.5 µm multimode fiber standard, other options available

Serial FPDP
Compliant to ANSI/VITA 17.1-2003, VITA 17.2 (draft 0.6)
Supports all framing modes (unframed, fixed size, dynamic size)
Supports flow control
Supports copy and copy/loop modes
Supports sync with and without data valid

PCI Local Bus
Compliant to IEEE 1386.1-2000 PCI Mezzanine Card (PMC)
Compliant to ANSI/VITA 39-2003
Compliant to PCI 2.3, PCI-X 1.0, up to 64-bits, 133 MHz
Supports 3.3V and 5V I/O signaling

PCI Express
Compliant to VITA 42.0 and ANSI/VITA 42.3-2006
Compliant to PCI Express 1.0a
Supports x1, x2, x4, x8 at 2.5 Gb/s per link

Mechanical
(L) 149mm (5.66”) x (W) 74mm (2.91”)


Power
Requires 5 Volts (PMC) or 5 to 12 Volt Vpwr (XMC), automatically selected
Typical Power: 15 Watts

For more information or to have a TEK Microsystems representative contact you please complete the information below.