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Tarvos-V5 (6 16-bit ADC, 1 16-bit DAC)
  • Overview
  • Features & Benefits
  • Details
  • Performance Specifications

Overview

The QuiXilica Tarvos-V5 VXS and Tarvos-V6 VXS boards are 6U ANSI/VITA 41 (VXS) compliant high-speed digitizer boards combining high density FPGA processing with six 16-bit A/D input channels at 185 MSPS (Megasamples per second) along with a coherent 16-bit D/A output channel.

By employing three Xilinx Virtex 5 FPGAs (Tarvos-V5) or three Virtex 6 FPGAs (Tarvos-V6), the result is unmatched FPGA processing density per channel, along with a measured signal-to-noise ratio (SNR) of 72 dBFS and Spurious Free Dynamic Range (SFDR) in excess of 95 dB.


QuiXilica Tarvos-V6
6 x 185 MSPS x 16-bit ADC
1 x 185 MSPS x 16-bit DAC

Tarvos-V5 Reduces System Size by 30%

Many advanced signal processing applications are based on antenna array processing and require large numbers of channels and distributed signal processing. The architecture of the Tarvos-V5 combines six analog input channels using the Linear Technologies LTC2209, with three Xilinx Virtex-5 FPGAs, providing up to 2,336 DSP slices and 1.285 TeraMAC/s of signal processing, equivalent to 61% of a Xilinx Virtex-5 SX95T device per input channel. For high channel count requirements such as beamforming, direction finding, jamming or anti-jam / interference cancellation, common in RADAR, SIGINT, communications, and EW applications, the Tarvos-V5 provides both the highest processing density per channel and per 6U slot, reducing total size, weight and power for many systems.

For example, in a phased array processor system with 20 I/Q inputs, where one FPGA is assigned to process data for each I/Q input channel, a traditional PMC or XMC based architecture would require 10 or even 20 slots depending on SBC selection and FPGA requirements. The same system can be implemented in 7 slots using the Tarvos-V5 VXS, using less space and power but still providing the same number of channels and 40% more FPGA processing capability than a 10 slot XMC-based system with 20 XMC modules using SX95T FPGAs.

The Tarvos-V5 features high bandwidth, low latency interconnect paths between its FPGAs which has been carefully specified to ensure that data from any analog channel can be broadcast to all FPGAs to support processing that relies on simultaneous access to data from all channels. This offers significant throughput advantages for a range of advanced multi-channel processing algorithms found in applications such as direction finding, STAP (Space Time Adaptive Processing) RADAR and Synthetic Aperature Radar (SAR) Image Formation.

The Tarvos-V5 is available for a wide range of operating environments, including commercial grade, rugged air and conduction cooled to support deployed applications such as unmanned airborne, naval and ground vehicles. For more information see the Rugged Data Sheet.

In addition to the Tarvos-V5, Tekmicro offers a broad range of Xilinx Virtex-5 based streaming I/O and FPGA processing solutions for both analog and digital I/O in a range of form factors.

Seven Channels: Six 16-bit ADC Inputs at 185 MSPS each, One 16-bit DAC Output at 185 MSPS
Multichannel Inputs in A Single Slot with On board DAC for Bi-directional signal flow
Six Digital IO Channels Running at Up to 3.75 Gb/s Using One QSFP and Two SFP+ Front Panel Connections
Flexible Data Movement Across the Front Panel For Use in Standard VME64 Environments
Dual 4x Full Duplex VXS Links and Two Full Duplex VITA 41.6 Ethernet Links
Enhanced VXS Capability
Three Xilinx Virtex-5 FPGAs: LXT, SXT or FXT for Each Location
Flexible FPGA Configuration Options for Each Location
Three GB DDR3 SDRAM Memory, (one GB per FPGA)
Unmatched FPGA Processing Density per Channel
Advanced Temperature & Current Monitoring
Protection From Damage and Usable in Customer Application
Comprehensive Developer’s Kit Provided Including FPGA Interface Cores, QuiXtart FPGA Utilities, Software and Reference Design
Faster Application Development
A Measured 72.31 dBFS Noise Floor with Greater Than 95 dB of SFD
Ideal for High Channel Count Signal Processing Applications
Convection or Conduction Cooled
Ruggedization Designed in For Demanding Deployed Applications

Front Panel High Speed Serial IO

Two SFP+ sites and one QSFP site are provided on the front panel which utilize standard fiber optic or 1000BaseT modules providing physical layer support for standard protocols such as Gigabit Ethernet, Serial FPDP (ANSI VITA 17.1 & 17.2), and Fibre Channel.

Virtex-5 FPGAs

Xilinx Virtex-5 FPGAs are the heart of the Tarvos-V5. The FPGAs interface between the ADC’s, memory and I/O resources to provide the user with a platform for implementing high performance real time processing. The Tarvos-V5 is configured with two SX95T FPGAs and an LX110T. Optionally developers can select an LX220T, SX240T, or FX100T FPGA to match resources to the application. For additional configuration options, contact the factory. All FPGAs are interconnected by wide parallel LVDS busses and also via high speed serial links using the Xilinx Rocket IO MGTs.


FPGAs A and B can be any FF1136 device. The Comms FPGA can be any FF1738 device.

VXS Backplane High Speed Serial IO

The Tarvos-V5 can be used as a VITA 41.0 payload card. Up to eight high speed serial links of up to 3.125 Gb/s full duplex data rates are supported via VITA 41.0 MultiGig RT2 P0 connector. Custom or standard communication protocols can be run over these links by providing appropriate firmware in the FPGA.

QuiXstart FPGA Configuration

A number of options are available for configuring the FPGA on the Tarvos-V5. For development purposes, a JTAG connection is available that allows users to configure the FPGA via standard Xilinx development tools. On board flash is available and can configure the FPGA on power up. TEK Microsystems’ QuiXstart tool also supports flexible configuration of the FPGA through a Gigabit Ethernet link from a remote server after a power up or reset event.

ADCs and DAC

Six channels of 185 MSPS, 16 bit resolution analog to digital conversion are provided on the Tarvos-V5. The input channels are based around the Linear Technologies LTC2209. The inputs are AC coupled and the input voltage level can be selected electronically to be either 1.5Vpp or 2.25Vpp to achieve best performance according to application requirements. One channel of 185 MSPS, 16 bit resolution digital to analog conversion is also provided. The output channel is based around the Maxim MAX5891. The output is AC coupled with full scale output voltage of -2dBm with a 50 ohm double-terminated load. All channels are simultaneously clocked with a 50 ohm, single ended clock input. The layout has been carefully designed to ensure phase matching of the clock across all input channels and to minimize aperture jitter. Trigger input and output connections are provided on the front panel to allow the hardware to be employed in a variety of radar and EW scenarios.

Memory

The Tarvos-V5 has two independent banks of on board double data rate (DDR3) SDRAM for each FPGA, providing a capacity of 512 MB in each bank, 1 GB total per FPGA. The on board memory can be clocked at rates up to 400 MHz, 800 MHz double data rate.
 

System Monitoring

The Tarvos-V5 board includes facilities to monitor current and temperature at various points on the board. Current monitoring of all main power rails is available. Die temperature monitoring of the three FPGAs and temperature monitoring of three locations on the PCB is also available. This allows a first level of protection to be implemented when the Tarvos-V5 is operating in a variety of different environmental scenarios. The output from the sensors will also be available to users through the COMMs FPGA firmware. The condition monitoring peripherals share an I2C bus along with the I2C bus from the COMMs FPGA to the QSFP module.

Front Panel Analog Signal Inputs
Quantity: 6 via SMA Connectors
Type: Single ended . Full Scale Input: -1.5Vpp/2.25Vpp into 50Ω. ADC pre-filtering provides optimal performance in the first Nyquist band. For alternate pre-filtering options switch for higher Nyquist band usage, please contact the factory

Front Panel Trigger Inputs
Quantity: 1 Pair of SSMC Edge-Launch Coaxial Connectors
Type: LVDS Termination: LVDS 100Ω differential terminated

External Clock
Quantity: 1 or (2) via (2) SMA Connectors
Single ended 50Ω terminated
Input Power Range: 2dBm (min) to 10dB (max)

Front Panel Analog Signal Output

Type: Single-Ended Full Scale. 1.5Vpp or 2.25Vpp programmable.
Resolution: 16-bits

A/D Converters

Quantity: 6
Sampling Rate: 185 MSPS
Resolution: 16 bits
Type: Linear Technologies LTC2209
Bandwidth: 800 MHz at full power

D/A Converter
Quantity: 1
Sampling Rate: 500 MSPS with maximum output of 185 MSPS. Slave to one clock.
Resolution: 16-bits
Type: Maxim MAX5891
Output Level: ±250mV or -2dBm for a sinusoidal output
Accuracy: ±5%

Memory
DDR3 SDRAM (2 banks per FPGA)
Size (STD): 512 MB per bank, 1 GB total per FPGA
Bus Width: 64 bits
Speed: 400 MHz, 800 MHz double data rate

Front Panel High Speed Serial Interface
2x SFP+ Ports: Providing (2) high-speed serial connections. Range of standard protocols, including Gigabit Ethernet and FibreChannel.

1x QSFP Port:
A quadruple SFP connector, of four independent lanes of high-speed serial. The lanes may be bonded together. The port supports a range of standard protocols: Gigabit Ethernet, FibreChannel and 10-Gigabit Ethernet (via 4-lane XAUI).

JTAG Port
Access to Virtex-5 FPGAs is available via custom JTAG cable assembly that interfaces with JTAG programming cable.

Size: Standard 6U VMEbus board, single slot; PCB:160mm (6.3”) x 233.5mm (9.2”)

Power: +5V, +3.3V, ±12V from VME64 backplane. Power consumption is dependent on customer application. Power estimating tools are available on request.