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Triton-V5 (1 10-bit ADC, 1 12-bit DAC)
  • Overview
  • Features & Benefits
  • Details
  • Performance Specifications


The QuiXilica Triton-V5 VXS is a 6U ANSI/VITA 41 (VXS) compliant high-speed digitizer board combines high density FPGA processing with one 10-bit A/D input channel performing at 2.2 GSPS (Gigasamples per second) colocated with one 12-bit DAC output channel performing at up to 4.0 GSPS.

By employing three Xilinx Virtex-5 FPGAs, Tekmicro’s Triton-V5 offers unmatched FPGA processing density per channel making it ideal for high channel count signal processing in applications.

QuiXilica Triton-V5
1 x 2.2 GSPS x 10-bit ADC
1 x 4.0 GSPS x 12-bit DAC

Triton-V5 Reduces System Size by 50%

The Triton-V5 includes a 2.2 GSPS analog input channel, an analog output channel of up to 4.0 Gsps based on the Euvis MD653D, and three Xilinx Virtex-5 FPGAs, providing up to 2,336 DSP slices and 1.3 TeraMAC/s of signal processing. Having ADC and DAC channels on a single board with high-density FPGA processing, Triton-V5 can reduce the number of boards in a system by up to 50%.

Triton-V5 transfers full sensor-rate data from the ADC processing (signal capture) to the DAC processing (waveform generation). This is an ideal solution for EW applications such as jammers and RADAR decoys.

The Triton-V5 features high bandwidth, low latency interconnect paths between its FPGAs. These have been carefully specified to ensure that data from the ADC input can be routed to the DAC output in support of low latency applications. Synchronization of ADC and DAC sampling on a single board, and on multiple boards, is done using an external trigger signal. This offers significant throughput advantages for a range of advanced processing algorithms including multi-channel algorithms found in applications such as direction finding, STAP (Space Time Adaptive Processing) RADAR, EW (jamming) and Synthetic Aperture Radar (SAR) Image Formation.

The Triton-V5 is available for a wide range of operating environments including commercial grade, rugged air, and conduction cooled to support deployed applications such as unmanned airborne, naval and ground vehicles. For more details see Tekmicro’s Rugged Data Sheet.

In addition to Triton-V5, Tekmicro offers a broad range of Xilinx Virtex-5 based streaming I/O and FPGA processing solutions for both analog and digital I/O in a range of form factors.

Two Channels: One 10-bit ADC Input at 2.2 GSPS, Co-located With One 12-bit DAC Output at up to 4.0 GSPS.
Achieves Ultra Low Latency From Acquisition to Response Critical to Jamming and RADAR Decoy Applications
First COTS Product to Achieve This Level of Performance.
Unprecedented Capability for Developers Requiring Ultra Wide Band Signal Generation
Sample Accurate Synchronization Across Multiple Boards.
Enables Solutions for New Multi-channel Applications
ADC and DAC Can Use Common Clock
Synchronization Across Mulltiple Boards or Independent Clocks
Six Digital IO Channels Running at Up to 3.75 Gb/s Using One QSFP and Two SFP+ Front Panel Connections
Flexible Data Movement Across the Front Panel For Use in Standard VME64 Environments
Dual 4x Full Duplex VXS Links and Two Full Duplex VITA 41.6 Ethernet Links
Enhanced VXS Capability
Three Xilinx Virtex-5 FPGAs: LXT, SXT or FXT for Each Location
Flexible FPGA Configuration Options for Each Location
Three GB DDR3 SDRAM Memory, (one GB per FPGA)
Unmatched FPGA Processing Density per Channel
Advanced Temperature & Current Monitoring
Protection From Damage and Usable in Customer Application
Comprehensive Developer’s Kit Provided Including FPGA Interface Cores, QuiXtart FPGA Utilities, Software and Reference Design
Faster Application Development
Convection or Conduction Cooled
Ruggedization Designed in For Demanding Deployed Applications


One channel of 2.2 GSPS, 10-bit resolution digital to analog conversion is provided on the Triton-V5 via the E2V AT84AS008. The input is AC coupled with a full scale input level of -2 dBm (0.5V p-p) into 50 ohms. The input may be single-ended or differential (factory build option).


One channel of up to 4.0 GSPS, 12-bit resolution digital to analog conversion is provided using the non-interpolating Euvis MD653D which has a bandwidth of 4 GHz.

The output is AC coupled and may be single-ended or differential (factory build option). Full scale output is -4 dBm (0.4V p-p) into 50 ohms. The DAC can be operated in normal-hold mode, or for extended operation into the 2nd Nyquist band, in Return to Zero (RZ) mode.

Virtex-5 FPGAs

Xilinx Virtex-5 FPGAs are the heart of the Triton-V5. The FPGAs interface between the ADC’s, memory and I/O resources to provide a platform for implementing high performance real time processing. The Triton-V5 is configured with two SX95T FPGAs and one LX110T FPGA. An LX220T, SX240T, or FX100T FPGA can be selected to match resources to the application. All FPGAs are interconnected by wide parallel LVDS busses and via high speed serial links using the Xilinx Rocket IO MGTs.

Front Panel High Speed Serial IO

Two SFP+ sites and one QSFP site are provided on the front panel which utilize standard fiber optic or 1000BaseT modules providing physical layer support for standard protocols such as Gigabit Ethernet, Serial FPDP (ANSI VITA 17.1 & 17.2), and Fibre Channel.

VXS Backplane High Speed Serial IO

The Triton-V5 can be used as a VITA 41.0 payload card. Up to eight high speed serial links of up to 3.125 Gb/s full duplex data rates are supported via VITA 41.0 MultiGig RT2 P0 connector. Custom or standard communication protocols can be run over these links by providing appropriate firmware in the FPGA.

QuiXstart FPGA Configuration

A number of options are available for configuring the FPGA on the Triton-V5. A JTAG connection is available to allow users to configure the FPGA via standard Xilinx development tools. On board flash is available and can configure the FPGA on power up. Tekmicro’s QuiXstart tool supports flexible configuration of the FPGA through a Gigabit Ethernet link from a remote server after a power up or reset event.


Trigger input connections are provided on the front panel to allow the hardware to be employed in a variety of radar and EW scenarios. The trigger input is LVDS (LVPECL is a factory build option). The DAC and ADC may use independent front panel triggers, or may us a single trigger source for synchronization of the two channels. Multiple Triton-V5 boards may be synchronized using the trigger input.


The ADC and DAC are clocked from separate or combined clock inputs (factory build option). The minimum input clock level is 6.0 dBm into 50 ohms.


The Triton-V5 has two independent banks of on board double data rate (DDR3) SDRAM for each FPGA, providing a capacity of 512 MB in each bank, 1 GB total per FPGA. The on board memory can be clocked at rates up to 400 MHz, 800 MHz double data rate.

System Monitoring

The Triton-V5 includes facilities to monitor current and temperature at various points on the board. Current monitoring of all main power rails is available. Die temperature monitoring of the three FPGAs and temperature monitoring of three locations on the PCB is also available. This allows a first level of protection when the Triton-V5 is operating in different environmental scenarios. The output from the sensors is available to users’ FPGA firmware applications, to allow the user application to adapt to changes in environmental conditions. The Triton-V5 also uses the system monitoring sensors to implement a system protection mechanism which will, independently of the users’ application, prevent excessive current or temperature from damaging the board.

A/D Converter
Quantity: 1
Sampling Rate: 2.2 GSPS
Resolution: 10-bits
Type: E2V AT84AS008
Bandwidth: 3.3 GHz at full power

D/A Converter
Quantity: 1
Sampling Rate: up to 4 GSPS
Resolution: 12-bits
Type: Euvis MD653D, operating in Normal Hold (NH)
Or Return to Zero (RZ) mode
Bandwidth: 4 GHz at full power

Front Panel Analog Signal Input and Output Quantity: 1 ADC and 1 DAC SMA Connectors
Type: Single ended. (Differential as factory build option)
ADC Full Scale Input: 0-5 V p-p into 50 Ω.
DAC Full Scale Output: -4 dBm with 50 Ω double-terminated load

Front Panel Trigger Inputs
Quantity: 1 or 2 via (2 or 4) SMA Connectors
Type: LVDS Termination: LVDS 100 Ω differential terminated.
Mode: Optional Independent Trigger inputs for ADC
Master/Slave: Single common trigger for both ADC and DAC

External Clock
Quantity: 1 or (2) via (2) SMA Connectors
Single ended 50Ω terminated
Input Power Range: 6 dBm (min) to 10 dBm (max)
Operating Modes: Clock Standalone / Master/Slave. Standalone: Use independent clock inputs for ADC and DAC inputs.
Master/Slave: Single common clock distributed to ADC and DAC

Front Panel Analog Signal Output
Type: Single-Ended Full Scale. 1.5Vpp or 2.25Vpp programmable.
Resolution: 16-bits

DDR3 SDRAM (2 banks per FPGA)
Size (STD): 512 MB per bank, 1 GB total per FPGA
Bus Width: 64 bits
Speed: 400 MHz, 800 MHz double data rate

Front Panel High Speed Serial Interface
2x SFP+ Ports: Providing (2) high-speed serial connections. Range of standard protocols, including Gigabit Ethernet and FibreChannel. Firmware supplied at additional cost.

1x QSFP Port: A quadruple SFP connector, of four independent lanes of high-speed serial. The lanes may be bonded together. The port supports a range of standard protocols: Gigabit Ethernet, FibreChannel and 10-Gigabit Ethernet (via 4-lane XAUI). Firmware supplied at additional cost.

Access to Virtex-5 FPGAs is available via custom JTAG cable assembly that interfaces with the JTAG programming cable.

Size: Standard 6U VMEbus board, single slot; PCB:160mm (6.3”) x 233.5mm (9.2”) Option: VXS P0 connector for backplane I/O

+5V, +3.3V, ±12V from VME64 backplane. Power consumption is dependent on customer application. Power estimating available on request.