Proteus-V5 VXS Two 10-bit ADCs at 5 GSPS
Datasheet (PDF)
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Two 10-bit ADCs at 5 GSPS
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Fastest 1st Nyquist sampling in a COTS product
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Also supports four channels @ 2.5 GSPS or eight channels @ 1.25 GSPS
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Implements multi-channel systems in fewer slots
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Three Xilinx Virtex®-5 FPGAs
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Acquisition and processing on a single card without backplane throughput limitations
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Single-ended or differential inputs
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Works with a range of RF receiver outputs
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Sample-accurate differential trigger input
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Supports coherent processing of a large number
of channels across multiple cards
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Six GB DDR3 SDRAM Memory
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Stores large amounts of data in real-time
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Single front panel clock input
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Simplifies external clock distribution
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Network interconnect through front panel SFP+
links, VITA 41.6 backplane, and P2 RTM
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Supports control plane via Gigabit Ethernet with all types of VME and VXS backplanes
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High speed serial I/O through front panel Quad
SFP, VXS P0, and VXS RTM
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High speed data plane interconnect in both VME (3.2 GB/s max) and VXS (5.7 GB/s standard, 9.8 GB/s max) applications
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| Advanced temperature & current monitoring |
Protects card from damage and enables pro-active health monitoring
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| Comprehensive Developer’s Kit provided including FPGA interface cores, QuiXstart FPGA utilities, software and reference designs |
Lowers development risk and accelerates time to market for user application |
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Convection or Conduction Cooled Options
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Leverages user firmware across laboratory and
deployed missions
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 TEK Microsystems has prepared a complete white paper
for download on the features and advantages of the QuiXilica V5 Architecture.
Overview
The QuiXilica Proteus-V5 VXS is a 6U VME and ANSI/VITA 41 (VXS) compliant high-speed digitizer board that combines high density FPGA processing with two 10-bit ADC devices, each of which can operate either as a single channel digitizing at up to 5 GSPS; two channels digitizing at up to 2.5 GSPS; or four channels digitizing at up to 1.25 GSPS.
By employing three Xilinx Virtex-5 FPGAs, Tekmicro’s Proteus-V5 combines ultra wideband signal acquisition with onboard high density FPGA processing. The result is a single slot solution that utilizes the latest ADC technology, supports advanced signal processing of up to 12.5 GB/s of digitized data, and forwards the results through a VME, RACE++, VXS or front panel connection to the next processing stage.
Proteus-V5 enables multi-channel signal acquisition systems with starting bandwidths of up to 2.5 GHz, with three Xilinx Virtex-5 FPGAs, providing up to 2,336 DSP slices and 1.3 TeraMAC/s of signal processing for front-end DSP, and can reduce the deployed size of multichannel systems by up to 50% compared to alternative solutions.
The Proteus-V5 features high bandwidth, low latency interconnect paths between its FPGAs. These have been carefully specified to ensure that data from all ADC inputs can be combined and processed together within the onboard FPGA resources, to support low-latency multi-channel applications such as adaptive beamforming.
Sample-accurate synchronization of ADC sampling on a single board, and between multiple boards, is done using an external trigger signal. This offers significant advantages in terms of channel matching performance for a range of advanced processing algorithms including multi-channel algorithms found in applications such as direction finding, STAP (Space Time Adaptive Processing) RADAR, EW, ELINT and Synthetic Aperture Radar (SAR) Image Formation.
 The Proteus-V5 is available for a wide range of operating environments including commercial grade, rugged air cooled, and conduction cooled to support deployed applications such as unmanned airborne, naval and ground vehicles. For more details see Tekmicro’s Ruggedization Data Sheet.
In addition to Proteus-V5, Tekmicro offers a broad range of Xilinx Virtex-5 based streaming I/O and FPGA processing solutions for both analog and digital I/O in a range of form factors. >> Read more.
Proteus-V5 VXS Details
 ADC
Proteus-V5 contains two EV10AQ190 quad 10-bit 1.25 GSPS ADCs. Each is configurable as either a single channel of 5 GSPS digitization; two channels of 2.5 GSPS digitization; or four channels of 1.25 GSPS digitization. The inputs are single-ended, AC coupled with a full scale input level of -2 dBm (nominal) into 50 ohms. As a build option, each ADC can be reconfigured with two differential, AC coupled inputs with a full scale input level of -5 dBm (nominal) into 100 ohms (differential). Click on the block diagram to enlarge.
Virtex-5 FPGAs
Xilinx Virtex-5 FPGAs are the heart of the Proteus-V5. The FPGAs interface to the ADC, memory, network and I/O resources to provide a platform for implementing high performance real time processing. The standard configuration of Proteus-V5 uses two SX95T-2 FPGAs and one LX110T-2 FPGA. Alternatively, an LX220T, LX330T, SX240T, FX100T or FX200T FPGA can be selected in place of the LX110T FPGA to match resources to the application. All FPGAs are interconnected by both wide parallel LVDS busses and high speed serial links using the Xilinx RocketIO MGTs.
Front Panel High Speed Serial I/O
Two SFP+ sites and one QSFP site are provided on the front panel which utilize standard fiber optic or 1000BaseT modules providing physical layer support for standard protocols such as Gigabit Ethernet and Serial FPDP (ANSI VITA 17.1 & 17.2). Specific protocol support requires the instantiation of appropriate firmware in the FPGAs. Consult the factory for protocol availability.
VXS Backplane High Speed Serial I/O
The Proteus-V5 can be used as a VITA 41.0 payload card. Up to eight high speed serial links of up to 3.125 Gb/s full duplex data rates are supported via VITA 41.0 MultiGig RT2 P0 connector. Custom or standard communication protocols such as Xilinx Aurora, Serial FPDP, or PCI Express can be run over these links by providing appropriate firmware in the FPGA.
QuiXstart FPGA Configuration
A number of options are available for configuring the FPGA on the Proteus-V5. A JTAG connection is available to allow users to configure the FPGA via standard Xilinx development tools. On board flash is available and can configure the FPGA on power up. Tekmicro’s QuiXstart tool may also be used to support flexible configuration of the FPGA through a Gigabit Ethernet link from a remote server after a power up or reset event.
Trigger
A trigger input is provided on the front panel to allow the hardware to be employed in a variety of radar and electronic warfare scenarios. The trigger input is differential, supporting inputs of ± 2.0 V, including LVDS and LVPECL. One trigger input serves all ADC channels, and is sampled using the same sampling clock as both ADCs, up to 5 GSPS. The trigger input may be used to synchronize the data streams from both ADCs on a single Proteus-V5 board, and to synchronize multiple Proteus-V5 boards to within a single sample period.
Clock
One sampling clock input serves all ADC channels, ensuring synchronous digitization of data by both ADCs. The sampling clock frequency is 2.5 GHz for a sampling rate of 5 GSPS (single channel mode). The minimum input clock level is -3 dBm (nominal) into 50 ohms.
Memory
The Proteus-V5 has two independent banks of onboard double data rate (DDR3) SDRAM for each FPGA, providing a capacity of 1 GB in each bank, 2 GB per FPGA, and 6 GB total. The onboard memory can be clocked at rates up to 400 MHz, equating to 800 MHz double data rate for throughput of 6.4 GB/s per bank.
System Monitoring
The Proteus-V5 includes facilities to monitor current and temperature at various points on the board. Current monitoring is implemented for all main power rails. Die temperature monitoring of the three FPGAs and ADCs, and temperature monitoring of three locations on the PCB is also supported. This provides an intelligent protection and monitoring system to allow Proteus-V5 to safely cover a wide range of operational requirements in the full range of environmental scenarios. The output from the sensors is available to users’ FPGA firmware applications, to allow the user application to adapt to changes in environmental conditions. The Proteus-V5 uses the system monitoring sensors to implement an intelligent system protection mechanism which will, independently of the users’ application, prevent excessive current or temperature from damaging the board.
PERFORMANCE SPECIFICATIONS
A/D Converter
Quantity: 2
Sampling Rate: Up to 5 GSPS (one channel per ADC), 2.5 GSPS (two channels per ADC), or 1.25 GSPS (four channels per ADC. Up to eight total channels.)
Resolution: 10 bits
Type: EV10AQ190 from E2V
Bandwidth: Up to 3 GHz
Front Panel Analog Signal Inputs
Quantity: 8 ADC SMA Connectors
Type: Single ended AC coupled.
ADC Full Scale Input: -2 dBm into 50 Ω.
Build option type: Differential AC coupled
Up to four differential AC-coupled inputs, with full scale input of -5 dBm into 100 Ω
Front Panel Trigger Inputs
Quantity: 1 via 2 SMA Connectors
Type: 100 Ω differentially terminated, ± 2V input level with hysteresis of 70 mV (includes support for LVDS and LVPECL)
Mode: Single common trigger for both ADCs
Front Panel GPIO
Quantity: 1 SMA Connector
Type: Directly routed to FPGA I/O pin, using 2.5 V LVCMOS
External Clock
Quantity: 1 SMA Connector
Type: Single ended 50Ω terminated
Input Power Range: -3 dBm (min) to 15 dBm (max)
Operating Modes: Single common clock distributed to both ADCs
Memory
DDR3 SDRAM (2 fully independent banks per FPGA)
Size: 1 GB per bank, 2 GB total per FPGA
Bus Width: 64 bits per bank
Speed: 400 MHz clock rate, equating to 800 MHz double data rate
Front Panel High Speed Serial Interface
2x SFP+ Ports: Providing (2) high speed serial connections. Range of standard protocols, including Gigabit Ethernet and Serial FPDP.
1x QSFP Port: A quadruple SFP connector, with four independent lanes of high-speed serial connections. The lanes may be bonded together. The port supports a range of standard protocols: Gigabit Ethernet, Serial FPDP and 10-Gigabit Ethernet (via 4-lane XAUI).
JTAG Port
Access to Virtex-5 FPGAs is available via custom JTAG cable assembly that interfaces with the standard Xilinx JTAG programming cable.
Size:
Standard 6U VMEbus board, single slot; PCB:160mm (6.3”) x 233.5mm (9.2”) Option: VXS P0 connector for backplane I/O
Power:
+5V, +3.3V, ±12V from VME64 backplane. Power consumption is dependent on customer application. Power estimation model is provided as part of the Developers Kit.
Contact factory for additional performance details.
For more information or to have a TEK Microsystems representative contact you please complete the information below.
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