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Atlas-V6 (8 12-bit ADC)
  • Overview
  • Features & Benefits
  • Details
  • Performance Specifications

Overview

The QuiXilica Atlas-V6 VXS is a 6U ANSI/VITA 41 (VXS) compliant high-speed digitizer board that combines high density FPGA processing with four or eight 12-bit ADC input channels performing at 1 GSPS (Gigasamples per second).
 


QuiXilica Atlas-V6 VME / VXS
8 x 1.0 GSPS x 12-bit

 

 

 

By employing three Xilinx Virtex-6 FPGAs, Tekmicro’s Atlas-V6 offers unmatched FPGA processing density per channel making it ideal for high channel count signal processing applications.

 

The Atlas-V6 includes eight 1 GSPS analog input channels and three Xilinx Virtex-6 FPGAs, providing up to 2,336 DSP slices and 1.3 TeraMAC/s of signal processing.

The Atlas-V6 features high bandwidth, low latency interconnect paths between its FPGAs. These have been carefully specified to ensure that data from all ADC inputs can be routed to the appropriate FPGA to meet the application processing requirements.

The ADCs are organized as two independent groups of four, each with their own clock and trigger inputs. However, a single clock and a single trigger input may be used for all eight channels on a single board. Synchronization of multiple boards is done using an external trigger signal. This offers significant throughput advantages for a range of advanced processing algorithms including coherent multi-channel algorithms found in applications such as direction finding, STAP (Space Time Adaptive Processing) Radar, EW (jamming) and Synthetic Aperture Radar (SAR) Image Formation.

The Atlas-V6 is available for a wide range of operating environments including commercial grade, rugged air, and conduction cooled to support deployed applications such as unmanned airborne, naval and ground vehicles. For more details see Tekmicro’s Ruggedization Data Sheet.

In addition to Atlas-V6, Tekmicro offers a broad range of Xilinx Virtex-6 based streaming I/O and FPGA processing solutions for both analog and digital I/O in a range of form factors.

Atlas-V6 Reduces System Size by 50%

8 Channels: 12-bit ADC input at 1 GSPS each

Achieves ultra low latency from acquisition to response critical to jamming and radar decoy applications

Sample accurate synchronization across multiple boards.

Enables solutions for new Multi-channel Applications

All 8 ADCs clocked from a common input, or 2 independent clock inputs for groups of 4 ADC channels

Interleaving applications for increased sampling rate

12 digital I/O channels running at up to 6.4 Gb/s using CXP front panel connection

Flexible data movement across the front panel for use in standard VME environments

One SFP port for Gigabit Ethernet connectivity

Network access and data movement to FPGAs via on-board Gigabit Ethernet switch

Dual 4x full duplex VXS Links and 2 full duplex VITA 41.6 Ethernet links

Enhanced VXS capability 

3 large pin count (1759 pin package) Xilink Virtex®-6 devices available per board (LX240, SX315, or SX 475). 

Matched FPGA processing and analog data bandwidth for dense channel-count systems

5 GB DDR3 SDRAM memory

Large memory resources for application flexibility

Comprehensive developer's kit provided including FPGA interface cores, QuiXstart FPGA utilities, software and reference designs 

Faster application development

ADC

Four or eight channels of up to 1 GSPS, 12-bit resolution analog to digital conversion is provided using the Texas Instruments ADS5400. The inputs are single-ended, AC coupled with a full scale input level of 10 dBm (2.0 V p-p) into 50 Ω.  

Virtex-6 FPGAs

Xilinx Virtex-6 FPGAs are the heart of the Atlas-V6. The FPGAs interface between the ADCs, memory and I/O resources to provide a platform for implementing high performance real time processing. The Atlas-V6 is configured with three high pin count Xilinx Virtex-6 devices (LX240, SX315, SX475) per board. Other device types can be used optionally or mixed for custom configurations.  All FPGAs are interconnected by wide parallel LVDS busses and via high speed serial links using the Xilinx Rocket IO MGTs.

Front Panel High Speed Serial IO

One 12-fiber CXP site is provided on the front panel for standard protocols such as Gigabit Ethernet, Serial FPDP (ANSI VITA 17.1 & 17.2), and Fibre Channel.  CXP module and breakout cables are available optionally for flexible I/O capability.  

On-Board Gigabit Ethernet Networking and Switching

An on-board Gigabit Ethernet Switch connected to each FPGA supports routing of control plane signaling and minimizes FPGA involvement for data distribution/forwarding between FPGAs.  A dedicated SFP port which supports both fiber and copper 1000BaseT Ethernet connects is available to connect to an outside network.

VXS Backplane High Speed Serial IO

The Atlas-V6 can be used as a VITA 41.0 payload card. Up to eight high speed serial links of up to 3.125 Gb/s full duplex data rates are supported via a VITA 41.0 MultiGig RT2 P0 connector. Custom or standard communication protocols can be run over these links by providing appropriate firmware in the FPGA.

High Speed Parallel LVDS Interconnectivity

All FPGAs are also interconnected with a number of LVDS pairs for optimized data transfer as the block diagram shows.

QuiXstart FPGA Configuration

A number of options are available for configuring the FPGAs on the Atlas-V6. A JTAG connection is available to allow users to configure the FPGAs via standard Xilinx development tools. On-board flash is available and can configure the FPGAs on power up. Tekmicro’s QuiXstart tool supports flexible configuration of the FPGAs through a Gigabit Ethernet link from a remote server after a power up or reset event.

Trigger

Trigger input connections are provided on the front panel to allow the hardware to be employed in a variety of radar and EW scenarios. The trigger inputs are LVDS (LVPECL is a factory build option). Each group of four ADC channels has its own trigger input, although one trigger input may be distributed to both groups of ADCs. Multiple Atlas-V6 boards may be synchronized to within one ADC sample period using the trigger input.

Clock

Each group of four ADC channels has its own clock input although a single clock input may be distributed to all eight ADC channels (factory build option). The minimum input clock level is -6 dBm into 50 ohms.

System Monitoring

The Atlas-V6 includes facilities to monitor current and temperature at various points on the board. Current monitoring of all main power rails is available. Die temperature monitoring of the three FPGAs and temperature monitoring of three locations on the PCB is also available. This allows a first level of protection when the Atlas-V6 is operating in different environmental scenarios. The output from the sensors is available to users’ FPGA firmware applications, to allow the user application to adapt to changes in environmental conditions. The Atlas-V6 also uses the system monitoring sensors to implement a system protection mechanism which will, independently of the users’ application, prevent excessive current or temperature from damaging the board.

Environmental/Ruggedization

In addition to providing high performance, Tekmicro boards and systems have been designed for ruggedization and power management. Tekmicro products operate effectively in laboratory, rugged air-cooled and rugged conduction-cooled environments to meet the needs of deployed applications.  > For more information on ruggedized products.

ADC Channels

Quantity: 4 or 8
Sampling Rate: up to 1 GSPS
Resolution: 12-bits
Type: TI ADS5400

Front Panel Analog Signal Input

Quantity: 8 ADC SSMC Connectors
Type: Single ended AC coupled
Full Scale Input: 0-2 V p-p (10 dBm) into 50 Ω

Front Panel Trigger Inputs

Quantity: 1 or 2 via (2 or 4) SSMC Connectors
Type: LVDS Termination: LVDS 100 Ω differential terminated. (LVPECL as factory build option)
Mode: Optional Independent Trigger inputs for each group of four ADCs
Master/Slave: Single common trigger for all 8 ADCs

External Clock

Quantity: 1 or (2) via (2) SSMC Connectors
Type:  Single ended 50Ω terminated
Input Power Range: -6 dBm (min) to 10 dBm (max)
Operating Modes: Clock Standalone / Master/Slave. Standalone: Use independent clock inputs for each group of 4 ADCs
Master/Slave: Single common clock distributed to all eight ADCs
Contact factory for additional performance details.

Memory

DDR3 SDRAM (2 banks per FPGA)
Front End FPGAs (each): 2 banks, 1 GB each, 64 bits, 6.4 GB/s
Back End FPGA: 2 banks, 512 MB each, 32 bits, 3.2 GB/s
Back End FPGA also has two banks of QDR-II SSRAM

Front Panel High Speed Serial Interface

CXP Port: A 12-fiber connector provides 12 independent full-duplex lanes
of high speed serial. Each lane supports up to 6.4 Gbps.

JTAG Port

Access to Virtex-6 FPGAs is available via custom JTAG cable assembly that interfaces with the JTAG programming cable.

Size

Standard 6U VMEbus board, single slot; PCB:160mm (6.3”) x 233.5mm (9.2”) Option: VXS P0 connector for backplane I/O

Power

+5V, +3.3V, ±12V from VME64 backplane. Power consumption is dependent on customer application. Power estimating available on request.

Contact factory for additional performance details.