The QuiXilica Proteus-V6 VXS is a 6U VME and ANSI/VITA 41 (VXS) compliant high-speed digitizer board that combines high density FPGA processing with two 10-bit ADC devices, each of which can operate either as a single channel digitizing at up to 5 GSPS; two channels digitizing at up to 2.5 GSPS; or four channels digitizing at up to 1.25 GSPS (Gigasamples per second).
QuiXilica Proteus-V6 VXS
2 x 5.0 GSPS x 10-bit ADC or
4 x 2.5 GSPS x 10-bit ADC or
8 x 1.25 GSPS x 10-bit ADC
By employing three Xilinx Virtex-6 FPGAs, Tekmicro’s Proteus-V6 combines high resolution wideband signal acquisition and generation with the onboard high density FPGA processing for a range of radar and Electronic Warfare applications such as target generation, jamming, and CM / CCM techniques. The result is a single slot solution that utilizes the latest ADC and DAC technology, supports advanced signal processing of up to 12.5 GB/s of digitized data, and forwards the results through VME, VXS or front panel connection via SFP+ or CXP to the next processing stage. Proteus-V6 enables multi-channel signal acquisition systems with staring bandwidths of up to 2.5 GHz, with three Xilinx Virtex-6 FPGAs, providing up to 6,048 DSP slices and 3.27 TeraMAC/s of signal processing for front end DSP, and can reduce the deployed size of multi-channel systems by up to 50% compared to alternative solutions.
The Proteus-V6 features high bandwidth, low latency interconnect paths between its FPGAs. These have been carefully specified to ensure that data from all ADC inputs can be routed to the appropriate FPGA to meet the application processing requirements. The ADCs are organized as two independent groups of four, each with their own clock and trigger inputs. However, a single clock and a single trigger input may be used for all eight channels on a single board. Synchronization of multiple boards is done using an external trigger signal. This offers significant throughput advantages for a range of advanced processing algorithms including coherent multi-channel algorithms found in applications such as direction finding, Space Time Adaptive Processing (STAP) radar, EW, ELINT and Synthetic Aperture Radar (SAR) image formation.
The Proteus-V6 is available for a wide range of operating environments including commercial grade, rugged air cooled, and conduction cooled to support deployed applications such as unmanned airborne, naval and ground vehicles. For more details, see Tekmicro’s Ruggedization Data Sheet.
In addition to Proteus-V6, Tekmicro offers a broad range of Xilinx Virtex-6 based streaming I/O and FPGA processing solutions for both analog and digital I/O in a range of form factors.
Two 10-bit ADCs at 5 GSPS
Fastest 1st Nyquist sampling in a COTS product
Also supports 4 channels @ 2.5 GSPS or 8 channels @ 1.25 GSPS
Implements multi-channel systems in fewer slots
Single-ended or differential inputs
Works with a range of RF receiver outputs
Sample-accurate differential trigger input
Supports coherent processing of a large number of channels across multiple cards
Single front panel clock input
Simplifies external clock distribution
Twelve fiber optic interfaces running at up to 6.4 Gb/s using CXP front panel connection
Flexible data movement across the front panel for use in standard VME environments
One SFP port for Gigabit Ethernet connectivity
Network access and data movement to FPGAs via on-board Gigabit Ethernet switch
Dual 4x full duplex VXS links and 2 full duplex VITA 41.6 ethernet links
Enhanced VXS capability
Three large pin count (1759 pin package) Xilinx Virtex®-6 devices available per board (LX240, SX315, or SX475). other configurations available
Matched FPGA processing and analog data bandwidth for dense channel count systems
5 GB DDR3 SDRAM Memory
Large memory resources for application flexibility
Two fully independent banks of (72 Mb/bank) QDRII+ memory on backend FPGA
Advanced temperature and current monitoring
Protection from damage and usable in customer applications
Comprehensive developer’s kit provided including FPGA interface cores, QuiXstart FPGA utilities, software and reference designs
Faster application development
Convection or conduction cooled options
Ruggedization designed in for demanding deployed applications
Proteus-V6 contains two EV10AQ190 quad 10-bit 1.25 GSPS ADCs from e2v. Each is configurable as either a single channel of 5 GSPS digitization; two channels of 2.5 GSPS digitization; or four channels of 1.25 GSPS digitization. The inputs are single ended, AC coupled with a full scale input level of 0 dBm into 50 Ω. As a build option, each ADC can be reconfigured with two differential, AC coupled inputs with a full scale input level of -5 dBm (nominal) into 100 Ω (differential).
Xilinx Virtex-6 FPGAs are the heart of the Proteus-V6. The FPGAs interface between the ADC’s, memory and I/O resources to provide a platform for implementing high performance real time processing. The Proteus-V6 is configured with three high pin count Xilinx Virtex-6 devices (LX240, SX315, or SX475) per board. Other device types can be used optionally or mixed for custom configurations. All FPGAs are interconnected by wide parallel LVDS busses and via high speed Aurora serial links using the Xilinx GTX transceivers.
Front Panel High Speed Serial I/O
One 12-fiber CXP site is provided on the front panel for standard protocols such as Gigabit Ethernet or Serial FPDP (ANSI VITA 17.1 & 17.2). CXP modules and breakout cables are available optionally for flexible I/O capability.
Onboard Gigabit Ethernet Networking and Switching
An onboard Gigabit Ethernet Switch connected to each FPGA supports routing of control plane signaling and minimizes FPGA involvement for data distribution/forwarding between FPGAs. A dedicated SFP port which supports both fiber and copper 1000 baseT ethernet connections is available to connect to an outside network.
VXS Backplane High Speed Serial I/O
The Proteus-V6 can be used as a VITA 41.0 payload card. Up to eight high speed serial links of up to 3.125 Gb/s full duplex data rates are supported via VITA 41.0 MultiGig RT2 P0 connector. Custom or standard communication protocols can be run over these links by providing appropriate firmware in the FPGA.
High Speed Parallel LVDS Interconnectivity
All FPGAs are also interconnected with a number of LVDS pairs for optimized data transfer as the block diagram shows.
QuiXstart FPGA Configuration
A number of options are available for configuring the FPGA on the Proteus-V6. A JTAG connection is available to allow users to configure the FPGA via standard Xilinx development tools. Onboard flash is available and can configure the FPGA on power up. Tekmicro’s QuiXstart tool supports flexible configuration of the FPGA through a Gigabit Ethernet link from a remote server after a power up or reset event.
Two Trigger inputs are provided on the front panel to allow the hardware to be employed in a variety of radar and electronic warfare scenarios. The trigger inputs are LVDS (LVPECL is a factory build option). The trigger inputs may be used to synchronize multiple Proteus-V6 boards to within a single sample period.
One clock input serves both ADC devices. The minimum input clock level is -6 dBm into 50 Ω.
The Proteus-V6 has two independent banks of onboard DDR3 SDRAM for each FPGA. The front end FPGAs have two 1 GB banks, each with throughput of 6.4 GB/s, while the back end FPGA has two 512 MB banks, each with throughput of 3.2 GB/s. The total memory capacity is 5 GB with aggregate throughput of 32 GB/s across six banks. All DDR3 memory banks are clocked at 400 MHz for an 800 MT/s transfer rate. In addition, there are two fully independent banks of QDRII+ SRAM memory for the back end FPGA. Each QDRII+ device has a 72 Mbit capacity (144 Mbit total) supported by an 18-bit data bus per bank.
For general purpose I/O signals, the Proteus-V6 can be accessed via the P2 connector and there is also an SSMC connector on the front panel which can be used for such things as a GPS signal, etc.
System Monitoring / Damage Protection
The Proteus-V6 includes facilities to monitor current and temperature at various points on the board. Current monitoring of all main power rails is available through the use of a Spartan-6 FPGA. Die temperature monitoring of the three FPGAs and temperature monitoring of three locations on the PCB is also available. This allows a first level of protection when the Proteus-V6 is operating in different environmental scenarios. The output from the sensors is available to the user’s FPGA firmware applications, to allow the application to adapt to changes in environmental conditions. The Proteus-V6 also uses the system monitoring sensors to implement a system protection mechanism which will, independently of the user’s application, prevent excessive current or temperature from damaging the board.
Quantity: 2 Sampling Rate: Up to 5 GSPS (one channel per ADC), 2.5 GSPS (two channels per ADC),
or 1.25 GSPS (four channels per ADC. Up to eight total channels) Resolution: 10-bits Type: EV10AQ190 from E2V Bandwidth: Up to 3 GHz
Front Panel Analog Signal Input
Quantity: 8 ADC SMA Connectors Type: Single ended AC coupled ADC Full Scale Input: 0 dBm into 50 ? Build option type: Differential AC coupled
Up to four differential AC coupled inputs, with full scale input of -5 dBm into 100 ?
Front Panel Trigger Inputs
Quantity: 1 via 2 SMA Connector Type: 100 Ω differential terminated, + 2V input level with hysteresis of 70 mV
Includes support for LVDS and LVPECL (build option) Mode: Single common trigger for both ADCs
Quantity: 1 SMA Connector Type: Single ended 50 Ω terminated Input Power Range: -3 dBm (min) to 15 dBm (max) Operating Modes: Single common clock distributed to both ADCs
Front panel SFP for fiber or copper Gigabit Ethernet
VITA 41.6 P0 interface for 1000 BASE-KX Gigabit Ethernet. Onboard Gigabit Ethernet switch
Access to Virtex-6 FPGAs is available via custom JTAG cable assembly that interfaces with the standard Xilinx JTAG programming cable.
DDR3 SDRAM (2 fully independent banks per FPGA) Size: 1 GB per front end bank, 512 MB total per back end bank Bus Width: 64-bits per front end bank, 32-bits per back end bank Speed: 400 MHz clock rate, 800 MT/s
QDRII + SRAM (2 fully independent banks for backend FPGA) Size: 72Mbits per backend bank (144Mbits total) Bus Width: 18-bits per bank Speed: Up to 500MHz clock rate
V6A - master, slave, A32:D32, A32:BLT, A32:MBLT, A32:2eSST
V6D - slave only, A32:D32, A32:BLT16 VXS Interface: P0 connector supports 8X high speed serial links on the backplane GPIO Interface: P2 connector Rear Transition Module (Optional): For rear access to the board, a Rear Transition Module is available that provides connections for GPIO connections, network access, PPS and trigger signals
Front Panel I/O
Gigabit Ethernet via SFP+
CXP supporting 12 fiber optic at up to 6.4 Gb/s per link
Standard ANSI / VITA 1.1-1997 (R2003) VMEbus board, 6U x 4HP, single 0.8” slot
Optional VXS P0 connector for backplane I/O
+5v, +3.3V, +12V from backplane. Power consumption is dependent on customer application. Power estimation Model is provided as part of the Developers Kit.
Contact factory for additional performance details.