The QuiXilica Pallene-V6 VME / VXS is a 6U VME and ANSI/VITA 41 (VXS) compliant high-speed digitizer board that combines high density FPGA processing with eight 12-bit Texas Instruments ADS54RF63 ADC devices, with rates up to 550 MSPS.
QuiXilica Pallene-V6 VME / VXS
8 x 550 MSPS x 10-bit ADC
By employing three Xilinx Virtex-6 FPGAs, Tekmicro’s Pallene-V6 combines ultra wideband signal acquisition with onboard high density FPGA processing. The result is a single slot solution that utilizes the latest ADC technology, supports advanced signal processing of up to 6.6 GB/s of digitized data, and forwards the results through a VME, RACE++, VXS or front panel connection to the next processing stage.
Pallene-V6 enables multi-channel signal acquisition systems with direct sampling of 275 MHz of bandwidth with an IF up to 2 GHz. Signal processing is performed by three Xilinx Virtex-6 FPGAs, providing up to 6,048 DSP slices and 7.2 TeraMAC/s of processing for front-end DSP.
The Pallene-V6 features high bandwidth, low latency interconnect paths between its FPGAs. These have been carefully specified to ensure that data from all ADC inputs can be combined and processed together within the onboard FPGA resources to support low-latency multi-channel applications such as adaptive beamforming using either the front end FPGAs or the back end FPGA.
Sample-accurate synchronization of ADC sampling on a single board, and between multiple boards, is done using an external trigger signal. This offers significant advantages in terms of channel matching performance for a range of advanced processing algorithms including multi-channel algorithms found in applications such as direction finding, STAP RADAR (Space Time Adaptive Processing) , EW, ELINT and SAR (Synthetic Aperture Radar) Image Formation.
The Pallene-V6 is available for a wide range of operating environments including commercial grade, rugged air cooled and conduction cooled to support deployed applications such as unmanned airborne, naval and ground vehicles. For more details see Tekmicro’s Ruggedization Data Sheet.
In addition to Pallene-V6, Tekmicro offers a broad range of FPGA-based streaming I/O and FPGA processing solutions for both analog and digital I/O in a range of form factors.
Pallene-V6 contains eight ADS54RF63 12-bit 550 MSPS ADCs. The inputs are single-ended, AC coupled with a full scale input level of +10 dBm into 50 Ω.
Xilinx Virtex-6 FPGAs are the heart of the Pallene-V6. The FPGAs interface between the ADC’s, memory and I/O resources to provide a platform for implementing high performance real time processing. The Pallene-V6 is configured with three high pin count Xilinx Virtex-6 devices (LX240, SX315, or SX475) per board. Other device types can be used optionally or mixed for custom configurations. All FPGAs are interconnected by wide parallel LVDS busses and via high speed serial links using the Xilinx GTX transceivers.
Front Panel High Speed Serial I/O
One 12-fiber CXP site is provided on the front panel for standard protocols such as Gigabit Ethernet, Serial FPDP (ANSI/VITA 17.1 & 17.2), and Fibre Channel. CXP modules and breakout cables are optionally available for flexible I/O capability.
On-Board Gigabit Ethernet Networking and Switching
An on-board Gigabit Ethernet switch connected to each FPGA supports routing of control plane signaling and minimizes FPGA involvement for data distribution/forwarding between FPGAs. A dedicated SFP port which supports both fiber and copper Gigabit Ethernet connections is available to connect to an outside network.
VXS Backplane High Speed Serial I/O
The Pallene-V6 can be used as a VITA 41.0 payload card. Up to eight high speed serial links of up to 3.125 Gb/s full duplex data rates are supported via VITA 41.0 MultiGig RT2 P0 connector. Custom or standard communication protocols can be run over these links by providing appropriate firmware in the FPGA.
QuiXstart FPGA Configuration
A number of options are available for configuring the FPGA on the Pallene-V6. A JTAG connection is available to allow users to configure the FPGA via standard Xilinx development tools. Onboard flash is available and can configure the FPGA on power up. Tekmicro’s QuiXstart tool supports flexible configuration of the FPGA through a Gigabit Ethernet link from a remote server after a power up or reset event.
Trigger input connections are provided on the front panel to allow the hardware to be employed in a variety of radar and EW scenarios. The trigger inputs are LVDS (LVPECL is a factory build option). The trigger inputs may be used to synchronize multiple Pallene-V6 boards to within a single sample period.
One clock input serves all ADC devices. The minimum input clock level is -6.7 dBm into 50 Ω.
The Pallene-V6 has two independent banks of onboard DDR3 SDRAM for each FPGA. The front end FPGAs have two 1 GB banks, each with throughput of 6.4 GB/s, while the back end FPGA has two 512 MB banks, each with throughput of 3.2 GB/s. The total memory capacity is 5 GB with aggregate throughput of 32 GB/s across six banks. All DDR3 memory banks are clocked at 400 MHz for an 800 MT/s transfer rate. In addition, there are two fully independent banks of QDRII+ SRAM memory for the back end FPGA. Each QDRII+ device has a 72 Mbit capacity (144 Mbit total) supported by an 18 bit data bus per bank.
System Monitoring / Damage Protection
The Pallene-V6 includes facilities to monitor current and temperature at various points on the board. Current monitoring of all main power rails is available through the use of a Spartan6 FPGA. Die temperature monitoring of the three FPGAs and temperature monitoring of three locations on the PCB is also available. This allows a first level of protection when the Pallene-V6 is operating in different environmental scenarios. The output from the sensors is available to users' FPGA firmware applications, to allow the user application to adapt to changes in environmental conditions. The Pallene-V6 also uses the system monitoring sensors to implement a system protection mechanism which will, independently of users' application, prevent excessive current or temperature from damaging the board.
In addition to providing high performance, Tekmicro boards and systems have been designed for ruggedization and power management. Tekmicro products operate effectively in laboratory, rugged air-cooled and rugged conduction-cooled environments to meet the needs of deployed applications. > For more information on ruggedized products.
Sampling Rate: Up to 550 MSPS
Type: ADS54RF63 from Texas Instruments
Bandwidth: Up to 2.3 GHz
Front Panel Analog Signal Input
Quantity: 8 ADC SMA Connectors
Type: Single ended AC coupled.
ADC Full Scale Input: +10 dBm into 50 Ω full scale
Front Panel Trigger Inputs
Quantity: 1 via 2 SSMC Connectors
Type: 100 Ω differential terminated hysteresis of 70 mV.
Includes support for LVDS (LVPECL as factory build option).
Mode: Single common trigger for ADCs
Quantity: 1 SSMC Connector
Type: Single ended 50Ω terminated
Input Power Range: 6.7 dBm (min) to +11.3 dBm (max)
Operating Modes: Single common clock distributed to ADCs
Front Panel High Speed Serial Interface
12x Fiber Optic Transceivers on CXP module
Up to 6.4 Gb/s, 8B/10B or 64/66 encoding
Range of standard protocols, including Gigabit Ethernet and Serial FPDP.
Front panel SFP for fiber or copper Gigabit Ethernet
VITA 41.6 P0 interface for 1000BASE-KX Gigabit Ethernet. Onboard Gigabit Ethernet switch
Per MIL-HDBK-217: 176,533 hours, Ground Benign environment
Access to Virtex-6 FPGAs is available via custom JTAG cable assembly that interfaces with the standard Xilinx JTAG programming cable.
DDR3 SDRAM (2 fully independent banks per FPGA)
Size: 1 GB per front end bank, 512 MB per back end bank
Bus Width: 64-bits per front end bank, 32 bits per back end bank
Speed: 400 MHz clock rate, 800 MT/s
QDRII+ SRAM (2 fully independent banks for backend FPGA)
Size: 72 Mbits per bank (144 Mbits total)
Bus Width: 18-bits per bank
Speed: Up to 500 MHz clock rate
VME Interface: D16/D32 slave interface, etc.
VXS Interface: P0 connector supports 8X high speed serial links on the backplane
GPIO Interface: P2 connector
RACE++ Interface (Optional): P2 Connector can be configured to support RACE++ environments
Rear Transition Module (Optional): For rear access to the board, a Rear Transition Module is available which provides connections for GPIO connections, network access, PPS, and trigger signals
Standard ANSI/VITA 1.1-1997 (R2003) VMEbus board, 6U x 4HP, single 0.8” slot
Optional VXS P0 connector for backplane I/O
+5V, +3.3V, ±12V from backplane. Power consumption is dependent on customer application. Power estimation model is provided as part of the Developers Kit.
Contact factory for additional performance details.