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Orion-V6 (2 12-bit DAC)
  • Overview
  • Features & Benefits
  • Details
  • Performance Specifications

Overview

The QuiXilica Orion-V6 VXS is a 6U VME and ANSI / VITA 41 (VXS) compliant high-speed digitizer board that combines high density FPGA processing with two 12-bit DAC output channels performing at up to 4.0 GSPS (Gigasamples per second).

QuiXilica Orion-V6 VME / VXS
2 x 4.0 GSPS x 12-bit DAC

By employing three Xilinx Virtex-6 FPGAs, Tekmicro’s Orion-V6 offers unmatched FPGA processing density per channel making it ideal for high channel count signal processing in applications such as Radar, target simulation and Electronic Warfare (EW).  The high bandwidth low latency interconnect provides advanced capability for high-density DSP for waveform generation. 

Each DAC is matched to an FPGA, leaving the third FPGA available for additional channel processing or system control functions.   Through a combination of hardware and firmware, Tekmicro has achieved sample-accurate synchronization for multiple channels across an entire chassis.  The sample accurate synchronization provides unprecedented accuracy for multi-channel signal generation applications such as threat simulation or beam steering.  

The Orion-V6 is available for a wide range of operating environments including commercial grade, rugged air cooled, and conduction cooled to support deployed applications such as unmanned airborne, naval and ground vehicles.  For more details, see Tekmicro’s Ruggedization Data Sheet.

In addition to Orion-V6, Tekmicro offers a broad range of Xilinx Virtex-6 based streaming I/O and FPGA processing solutions for both analog and digital I/O in a range of form factors.

 

20141007

 

Two 12-bit DACs channels at up to 4.0 GSPS

First COTS product to achieve this level of performance

Phase matched DAC outputs Ultra wideband signal generation ideal for IQ waveform generation

Sample accurate synchronization across multiple boards.

Enables solutions for new multi-channel applications

Twelve fiber optic interfaces running at up to 6.4 Gb/s using CXP front panel connection

Flexible data movement across the front panel for use in standard VME environments

One SFP port for Gigabit Ethernet connectivity

Network access and data movement to FPGSs via on-board Gigabit Ethernet switch

Dual 4x full duplex VXS links and 2 full duplex VITA 41.6 ethernet link

Enhanced VXS capability

Three large pin count (1759 pin package) Xilinx Virtex®-6 devices available per board (LX240, SX315, or SX475). other configurations available

Matched FPGA processing and analog data bandwidth for dense channel count systems 

5 GB DDR3 SDRAM Memory

Large memory resources for application flexibility

Two fully independent banks of (72 Mb/bank) QDRII+ memory on backend FPGA  

Advanced temperature and current monitoring

Protection from damage and usable in customer applications

Comprehensive developer’s kit provided including FPGA interface cores, QuiXstart FPGA utilities, software and reference designs Faster application development

Convection or conduction cooled options

Ruggedization designed in for demanding deployed applications

 

DAC

The Orion-V6 contains two MD653D 12-bit resolution digital to analog conversion from Euvis, which has a bandwidth of 4 GHz.   Each of the two channels of up to 4.0 GSPS,  The output is AC coupled and may be single-ended or differential (factory build option).  The full scale output is 2 dBm (0.4V p-p) into 50 Ω. The DAC may be operated in normal-hold mode, or for extended operation into the 2nd Nyquist band, in Return to Zero (RZ) mode.

Virtex-6 FPGAs

Xilinx Virtex-6 FPGAs are the heart of the Orion-V6. The FPGAs interface between the DACs and I/O resources to provide a platform for implementing high performance real time processing. The Orion-V6 is configured with three high pin count Xilinx Virtex-6 devices (LX240, SX315 or SX475) per board. Other device types can be used optionally or mixed for custom configurations. All FPGAs are interconnected by wide parallel LVDS busses and via high speed Aurora serial links using the Xilinx GTX transceivers.

Front Panel High Speed Serial I/O

One 12-fiber CXP site is provided on the front panel for standard protocols such as Gigabit Ethernet or Serial FPDP (ANSI / VITA 17.1 & 17). CXP modules and breakout cables are optionally available for flexible I/O capability.

Onboard Gigabit Ethernet Networking and Switching

An onboard Gigabit Ethernet Switch connected to each FPGA supports routing of control plane signaling and minimizes FPGA involvement for data distribution/forwarding between FPGAs. A dedicated SFP port which supports both fiber and copper 1000 baseT ethernet connections is available to connect to an outside network.

VXS Backplane High Speed Serial I/O

The Orion-V6 can be used as a VITA 41.0 payload card. Up to eight high speed serial links of up to 3.125 Gb/s full duplex data rates are supported via the VITA 41.0 MultiGig RT2 P0 connector. Custom or standard communication protocols can be run over these links by providing appropriate firmware in the FPGA.

High Speed Parallel LVDS Interconnectivity 

All FPGAs are also interconnected with a number of LVDS pairs for optimized data transfer as the block diagram shows.

QuiXstart FPGA Configuration

A number of options are available for configuring the FPGA on the Orion-V6. A JTAG connection is available to allow users to configure the FPGA via standard Xilinx development tools. Onboard flash memory is available and can configure the FPGA on power up. Tekmicro’s QuiXstart tool supports flexible configuration of the FPGA through a Gigabit Ethernet link from a remote server after a power up or reset event.

Trigger

Trigger input connections are provided on the front panel to allow the hardware to be employed in a variety of radar and electronic warfare scenarios. The trigger input is differential, supporting LVDS and LVPECL (as a build option).  Each channel can operate with its own trigger, or one trigger can be used for both DAC channels. The trigger inputs may be used to synchronize multiple Orion-V6 boards to within a single sample period.

Clock

Clock inputs are provided on the front panel.  Each channel can operate with its own clock, or one clock can be used for both DAC channels (factory build option). The minimum input clock level is 6.0 dBm into 50Ω.  When using a single clock, the two DACs receive a phase-aligned clock.

Memory

The Orion-V6 has two independent banks of onboard DDR3 SDRAM for each FPGA.  The front end FPGAs have two 1 GB banks, each with throughput of 6.4 GB/s, while the back end FPGA has two 512 MB banks, each with throughput of 3.2 GB/s.  The total memory capacity is 5 GB with aggregate throughput of 32 GB/s across six banks.  All DDR3 memory banks are clocked at 400 MHz for an 800 MT/s transfer rate. In addition, there are two fully independent banks of QDRII+ SRAM memory for the back end FPGA. Each QDRII+ device has a 72 Mbit capacity (144 Mbit total) supported by an 18-bit data bus per bank.

GPIO Connections

For general purpose I/O signals, the Atlas-V6 can be accessed via the P2 connector and there is also an SSMC connector on the front panel which can be used for such things as a GPS signal, etc.

System Monitoring / Damage Protection

The Orion-V6 includes facilities to monitor current and temperature at various points on the board. Current monitoring of all main power rails is available through the use of a Spartan-6 FPGA.  Die temperature monitoring of the three FPGAs and temperature monitoring of three locations on the PCB is also available. This allows a first level of protection when the Orion-V6 is operating in different environmental scenarios. The output from the sensors is available to the user’s FPGA firmware applications, to allow the application to adapt to changes in environmental conditions. The Orion-V6 also uses the system monitoring sensors to implement a system protection mechanism which will, independently of the user’s application, prevent excessive current or temperature from damaging the board.

D/A Converter

Quantity: 2 channel
Sampling Rate: up to 4.0 GSPS each
Resolution: 12-bits
Type:  Euvis M653D
Bandwidth: Up to 4.0 GHz

Front Panel Trigger Inputs

Quantity: 1 or 2 via SMA Connectors
Type: 100 Ω differentially terminated, support for LVDS and LVPECL (build option)
Mode: Independent or Master/Slave

Clock

Quantity: 1 or 2 via SMA connectors
Type: Single ended 50 Ω terminated
Input Power Range: +6.0 dBm (min) to +10.0 dBm (max)
Modes: Independent or Master/Slave

Network Interface

Front panel SFP for fiber or copper Gigabit Ethernet
VITA 41.6 P0 interface for 1000 BASE-KX Gigabit Ethernet
Onboard Gigabit Ethernet switch

Memory

DDR3 SDRAM (2 fully independent banks per FPGA)
Size: 1 GB per front end bank, 512 MB per back end bank
Bus Width: 64-bits per front end bank, 32-bits per back end bank
Speed: 400 MHz clock rate, 800 MT/s

QDR II+ SRAM (2 fully independent banks for back end FPGA)
Size: 72 Mbits per bank (144 Mbits total)
Bus Width: 18-bits per bank
Speed: Up to 500 MHz clock rate

Backplane I/O

VME Interface: 
V6A - master, slave, A32:D32, A32:BLT, A32:MBLT, A32:2eSST
V6D - slave only, A32:D32, A32:BLT16
VXS Interface: P0 connector supports 8X high speed serial links 
GPIO Interface: P2 connector 
Rear Transition Module (Optional): For rear access to the board, a Rear Transition Module is available that provides connections for GPIO connections, network access, PPS and trigger signals

Front Panel I/O

Gigabit Ethernet via SFP+
CXP supporting 12 fiber optic at up to 6.4 Gb/s per link

Size

Standard ANSI / VITA 1.1-1997 (R2003) VMEbus board, 6U x  4HP, single 0.8” slot
Optional VXS P0 connector for backplane I/O

Power

+5V, +3.3V, ±12V from backplane. Power consumption is dependent on customer application. Power estimation model is provided as part of the Developers Kit.

Contact factory for additional performance details.