Standardized in 1994, the RACE(tm) architecture from Mercury Computer Systems was one of the first switched fabrics using crossbar technology to deliver scalable bandwidth for high performance embedded systems.
The second generation of RACEway Interconnect, RACE++, was introduced in 1999 and offers up to 533 MB/s per 6U slot while maintaining backwards
compatibility with RACEway 1.0 and single port systems.
Tekmicro's PowerRACE family of intelligent I/O controllers was first introduced in 1999 and was both the first 3rd party RACE++ solution and also the first RACEway-enabled PMC carrier to use PowerPC technology. All PowerRACE models have an onboard crossbar to provide a highly flexible and scalable architecture for streaming I/O within a common framework. Each I/O node is completely independent, decoupling the two PMC sites from each other and eliminating both software complexity and throughput bottlenecks.
For MCOE users, PowerRACE is available with a DX-like API for a wide range of supported PMC I/O modules, including Fibre Channel for both JBOD/RAID storage and for point-to-point links, along with various application-specific solutions.
Tekmicro has shipped over a thousand PowerRACE boards to customers worldwide.
With the continuing trend of industry consolidation reducing the number of options available to systems integrators, Tekmicro continues to support both existing and new customers with the highest performance RACE++ streaming I/O solutions, along with a lifecycle support commitment through 2015 for technology refresh and new program requirements.
Standardized in 1994, the RACE(tm) architecture from Mercury Computer Systems was one of the first switched fabrics using crossbar technology to deliver scalable bandwidth for high performance embedded systems.
